DF2117RVLP20HV Renesas Electronics America, DF2117RVLP20HV Datasheet - Page 7

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DF2117RVLP20HV

Manufacturer Part Number
DF2117RVLP20HV
Description
MCU 16BIT FLASH 3V 160K 144-LGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2117RVLP20HV

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Part Number
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Quantity
Price
Part Number:
DF2117RVLP20HV
Quantity:
2 122
Item
1.1.1 Features
2.2.22 CLRMAC
Operand Format and
Number of States
Required for Execution
2.2.24 DAA
Description
2.2.37
Operand Format and
Number of States
Required for Execution
2.2.42 (1) MULXS (B)
Operand Format and
Number of States
Required for Execution
2.2.42 (2) MULXS (W)
Operand Format and
Number of States
Required for Execution
2.2.43 (1) MULXU (B)
Operand Format and
Number of States
Required for Execution
2.2.43 (2) MULXU (W)
Operand Format and
Number of States
Required for Execution
LDMAC
Main Revisions for This Edition
Page
2
90
94
130
151
152
153
154
Revisions (See Manual for Details)
Note * added
— Maximum clock frequency: 20 MHz *
Note: * The maximum operating frequency and instruction
execution time differ depending on the product.
Further explanation added to note
The number of states may differ depending on the product.
For details, refer to the hardware manual of the product in
question.
Table amended
Further explanation added to note
The number of states may differ depending on the product.
For details, refer to the hardware manual of the product in
question.
Adjustment
C Flag
before
0
1
1
1
Upper 4 Bits
Adjustment
before
A to F
0 to 2
0 to 2
0 to 3
Adjustment
H Flag
before
Rev. 4.00 Feb 24, 2006 page v of xiv
1
0
0
1
Lower 4 Bits
Adjustment
before
A to F
0 to 3
0 to 9
0 to 3
(Hexadecimal)
Added
Value
66
60
66
66
Adjustment
C Flag
after
1
1
1
1

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