HD6473837FV Renesas Electronics America, HD6473837FV Datasheet - Page 230
HD6473837FV
Manufacturer Part Number
HD6473837FV
Description
IC H8/3837 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD6473837HV.pdf
(562 pages)
Specifications of HD6473837FV
Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
84
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Eeprom Size
-
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-BQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6473837FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6473837FV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Input capture register GF (ICRGF)
ICRGF is an 8-bit read-only register. When the falling edge of the input capture signal is detected,
the TCG value at that time is transferred to ICRGF. If the input capture interrupt select bit (IIEGS)
is set to 1 in TMG, bit IRRTG in interrupt request register 2 (IRR2) is set to 1. If in addition bit
IENTG in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt is requested. Details on
interrupts are given in 3.3, Interrupts.
To ensure proper input capture when the noise canceller is not used, the pulse width of the input
capture signal should be at least 2 or 2
Upon reset, ICRGF is initialized to H'00.
Input Capture Register GR (ICRGR)
ICRGR is an 8-bit read-only register. When the rising edge of the input capture signal is detected,
the TCG value at that time is sent to ICRGR. If the IIEGS bit is cleared to 0 in TMG, bit IRRTG
in interrupt request register 2 (IRR2) is set to 1. If in addition bit IENTG in interrupt enable
register 2 (IENR2) is set to 1, a CPU interrupt is requested. Details on interrupts are given in 3.3,
Interrupts.
To ensure proper input capture when the noise canceller is not used, the pulse width of the input
capture signal should be at least 2 or 2
Upon reset, ICRGR is initialized to H'00.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0
ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0
R
R
7
0
7
0
R
R
6
0
6
0
SUB
SUB
R
R
5
0
5
0
.
.
R
R
4
0
4
0
R
R
3
0
3
0
R
R
2
0
2
0
R
R
1
0
1
0
R
R
0
0
0
0
213
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