HD6473837FV Renesas Electronics America, HD6473837FV Datasheet - Page 272

• Manufacturer Part Number: HD6473837FV
• Description: IC H8/3837 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473837FV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 84
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Eeprom Size: -
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-BQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial Control Register 3 (SCR3)
Serial control register 3 (SCR3) is an 8-bit register that controls SCI3 transmit and receive
operations, enables or disables serial clock output in asynchronous mode, enables or disables
interrupts, and selects the serial clock source. SCR3 can be read and written by the CPU at any
time.
SCR3 is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
Bit 7—Transmit Interrupt Enable (TIE): Bit 7 enables or disables the transmit data empty
interrupt (TXI) request when data is transferred from TDR to TSR and the transmit data register
empty bit (TDRE) in the serial status register (SSR) is set to 1. The TXI interrupt can be cleared
by clearing bit TDRE to 0, or by clearing bit TIE to 0.
Bit 7: TIE
0
1
Bit 6—Receive Interrupt Enable (RIE): Bit 6 enables or disables the receive error interrupt
(ERI), and the receive data full interrupt (RXI) requested when data is transferred from RSR to
RDR and the receive data register full bit (RDRF) in the serial status register (SSR) is set to 1.
There are three kinds of receive error: overrun, framing, and parity. RXI and ERI interrupts can be
cleared by clearing SSR flag RDRF, or flags FER, PER, and OER to 0, or by clearing bit RIE to 0.
Bit 6: RIE
0
1
Bit
Initial value
Read/Write
R/W
Description
Transmit data empty interrupt request (TXI) disabled
Transmit data empty interrupt request (TXI) enabled
Description
Receive data full interrupt request (RXI) and receive error interrupt request
(ERI) disabled
Receive data full interrupt request (RXI) and receive error interrupt request
(ERI) enabled
TIE
7
0
R/W
RIE
6
0
R/W
TE
5
0
R/W
RE
4
0
MPIE
R/W
3
0
TEIE
R/W
2
0
CKE1
R/W
1
0
(initial value)
(initial value)
CKE0
R/W
0
0
255