MT48LC32M8A2P-7E:DTR Micron Technology Inc, MT48LC32M8A2P-7E:DTR Datasheet - Page 32
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MT48LC32M8A2P-7E:DTR
Manufacturer Part Number
MT48LC32M8A2P-7E:DTR
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT48LC32M8A2P-7EDTR.pdf
(87 pages)
Specifications of MT48LC32M8A2P-7E:DTR
Lead Free Status / Rohs Status
Compliant
- Current page: 32 of 87
- Download datasheet (4Mb)
NO OPERATION (NOP)
LOAD MODE REGISTER (LMR)
ACTIVE
Figure 13: ACTIVE Command
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
The NO OPERATION (NOP) command is used to perform a NOP to the selected device
(CS# is LOW). This prevents unwanted commands from being registered during idle or
wait states. Operations already in progress are not affected.
The mode registers are loaded via inputs A[n:0] (where An is the most significant ad-
dress term), BA0, and BA1(see Mode Register (page 45)). The LOAD MODE REGISTER
command can only be issued when all banks are idle and a subsequent executable com-
mand cannot be issued until
The ACTIVE command is used to activate a row in a particular bank for a subsequent
access. The value on the BA0, BA1 inputs selects the bank, and the address provided
selects the row. This row remains active for accesses until a PRECHARGE command is
issued to that bank. A PRECHARGE command must be issued before opening a differ-
ent row in the same bank.
BA0, BA1
Address
RAS#
CAS#
WE#
CKE
CLK
CS#
HIGH
Bank address
Row address
t
32
MRD is met.
Don’t Care
Micron Technology, Inc. reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16 SDRAM
© 1999 Micron Technology, Inc. All rights reserved.
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