MT48LC32M8A2P-7E:DTR Micron Technology Inc, MT48LC32M8A2P-7E:DTR Datasheet - Page 77

MT48LC32M8A2P-7E:DTR

Manufacturer Part Number
MT48LC32M8A2P-7E:DTR
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT48LC32M8A2P-7E:DTR

Lead Free Status / Rohs Status
Compliant
Command
Figure 48: WRITE Without Auto Precharge
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
BA0, BA1
Address
DQM
CKE
A10
CLK
DQ
t CMS
t CKS
t AS
t AS
t AS
Bank
ACTIVE
Row
Row
T0
t CKH
t CMH
t AH
t AH
t AH
t RCD
t RAS
t RC
t CK
Note:
T1
NOP
Disable auto precharge
1. For this example, BL = 4 and the WRITE burst is followed by a manual PRECHARGE.
t CMS
t CL
Column m
t DS
WRITE
Bank
T2
D
IN
t CMH
t DH
t CH
t DS
T3
NOP
D
IN
t DH
t DS
T4
NOP
D
IN
t DH
77
t DS
NOP
T5
D
IN
t DH
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t WR
NOP
T6
256Mb: x4, x8, x16 SDRAM
PRECHARGE
Single bank
All banks
PRECHARGE Operation
Bank
T7
© 1999 Micron Technology, Inc. All rights reserved.
t RP
NOP
T8
ACTIVE
Row
Row
Bank
T9
Don’t Care

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