MT48LC32M8A2P-7E:DTR Micron Technology Inc, MT48LC32M8A2P-7E:DTR Datasheet - Page 75

• Manufacturer Part Number: MT48LC32M8A2P-7E:DTR
• Manufacturer: Micron Technology Inc

Specifications of MT48LC32M8A2P-7E:DTR

• Lead Free Status / Rohs Status: Compliant

Figure 45: WRITE With Auto Precharge Interrupted by a READ
Figure 46: WRITE With Auto Precharge Interrupted by a WRITE
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Internal
States
Internal
States
Command
Command
Note:
Note:
Address
Address
Bank m
Bank m
Bank n
Bank n
CLK
CLK
DQ
DQ
1. DQM is LOW.
1. DQM is LOW.
Page active
Page active
NOP
T0
T0
NOP
WRITE - AP
WRITE - AP
Page active
Bank n,
Page active
Bank n,
Bank n
Bank n
Col a
T1
D
T1
Col a
D
IN
IN
WRITE with burst of 4
WRITE with burst of 4
T2
T2
NOP
D
NOP
D
IN
IN
75
READ - AP
Bank m,
T3
T3
Col d
Bank m
D
NOP
IN
Interrupt burst, write-back
t
WR - bank n
READ with burst of 4
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WRITE - AP
Bank m,
Col d
T4
Bank m
T4
D
NOP
CL = 3 (bank m)
t
Interrupt burst, write-back
WR - bank n
IN
WRITE with burst of 4
T5
T5
NOP
NOP
D
256Mb: x4, x8, x16 SDRAM
t
IN
Precharge
RP - bank n
PRECHARGE Operation
T6
T6
NOP
D
NOP
D
OUT
t RP - bank n
Precharge
IN
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Don’t Care
Don’t Care
T7
T7
D
NOP
NOP
D
t WR - bank m
OUT
t RP - bank m
IN
Write-back