MT48LC32M8A2P-7E:DTR Micron Technology Inc, MT48LC32M8A2P-7E:DTR Datasheet - Page 57
![](/photos/40/76/407675/tsop-ii-54_sml.jpg)
MT48LC32M8A2P-7E:DTR
Manufacturer Part Number
MT48LC32M8A2P-7E:DTR
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT48LC32M8A2P-7EDTR.pdf
(87 pages)
Specifications of MT48LC32M8A2P-7E:DTR
Lead Free Status / Rohs Status
Compliant
- Current page: 57 of 87
- Download datasheet (4Mb)
Figure 27: Alternating Bank Read Accesses
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Command
BA0, BA1
Address
DQM
CLK
CKE
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
Bank 0
T0
Row
Row
t CKH
t CMH
t AH
t AH
t AH
t RCD - bank 0
t RAS - bank 0
t RC - bank 0
t RRD
t CK
Note:
T1
NOP
1. For this example, BL = 4 and CL = 2.
Enable auto precharge
t CMS
t CL
Column m
Bank 0
T2
READ
t CMH
t CH
CL - bank 0
T3
NOP
t LZ
t AC
57
ACTIVE
Bank 3
T4
Row
Row
D
OUT
t OH
t AC
t RCD - bank 3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T5
D
NOP
OUT
t OH
t AC
Enable auto precharge
256Mb: x4, x8, x16 SDRAM
Column b
Bank 3
T6
READ
D
OUT
t OH
t AC
1
t RP - bank 0
CL - bank 3
© 1999 Micron Technology, Inc. All rights reserved.
T7
NOP
D
READ Operation
Don’t Care
OUT
t OH
t AC
Bank 0
Row
Row
T8
ACTIVE
D
OUT
t OH
t RCD - bank 0
Undefined
t AC
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