MT48LC32M8A2P-7E:DTR Micron Technology Inc, MT48LC32M8A2P-7E:DTR Datasheet - Page 69

• Manufacturer Part Number: MT48LC32M8A2P-7E:DTR
• Manufacturer: Micron Technology Inc

Specifications of MT48LC32M8A2P-7E:DTR

• Lead Free Status / Rohs Status: Compliant

Figure 39: READ With Auto Precharge Interrupted by a READ
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Internal
states
Command
Note:
Address
Bank m
Bank n
CLK
DQ
registered. The last valid data WRITE to bank n will be data registered one clock prior to
a WRITE to bank m (see Figure 46 (page 75)).
1. DQM is LOW.
Page active
NOP
T0
READ - AP
Page active
Bank n,
Bank n
T1
Col a
READ with burst of 4
T2
CL = 3 (bank n)
NOP
69
READ - AP
Bank m,
T3
Bank m
Col d
Interrupt burst, precharge
READ with burst of 4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T4
CL = 3 (bank m)
NOP
t
RP - bank n
D
OUT
T5
NOP
256Mb: x4, x8, x16 SDRAM
D
OUT
PRECHARGE Operation
T6
NOP
D
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OUT
Idle
T7
Don’t Care
NOP
t RP - bank m
D
Precharge
OUT