DS21552L+ Maxim Integrated Products, DS21552L+ Datasheet - Page 19

• Manufacturer Part Number: DS21552L+
• Description: IC TXRX T1 1-CHIP 5V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21552L+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.1.2 RECEIVE SIDE PINS (cont.)
Signal Name:
Signal Description:
Signal Type:
An extracted 8 kHz pulse, one RCLK wide, is output at this pin which identifies frame boundaries.
Signal Name:
Signal Description:
Signal Type:
Only used when the receive side elastic store is enabled. An extracted pulse, one RSYSCLK wide, is output at this pin which
identifies multiframe boundaries. If the receive side elastic store is disabled, then this output will output multiframe boundaries
associated with RCLK.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of RCLK with the data out of the receive side framer.
Signal Name:
Signal Description:
Signal Type:
1.544 MHz , 2.048 MHz , 4.096 MHz or 8.192 MHz clock. Only used when the receive side elastic store function is enabled.
Should be tied low in applications that do not use the receive side elastic store. See section 20 on page 129 for details on 4.096
MHz and 8.192 MHz operation using the Interleave Bus Option.
Signal Name:
Signal Description:
Signal Type:
Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic store is disabled.
Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
A dual function output that is controlled by the CCR3.5 control bit. This pin can be programmed to either toggle high when the
synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for 5 msec.
Signal Name:
Signal Description:
Signal Type:
Set high when the line interface detects a carrier loss.
Signal Name:
Signal Description:
Signal Type:
Set high when the signaling data is frozen via either automatic or manual intervention. Used to alert downstream equipment of
the condition.
4.1.2 RECEIVE SIDE PINS (cont.)
Signal Name:
Signal Description:
Signal Type:
An 8.192MHz clock output that is referenced to the clock that is output at the RCLK pin.
Signal Name:
Signal Description:
Signal Type:
RFSYNC
Receive Frame Sync
Output
RMSYNC
Receive Multiframe Sync
Output
RDATA
Receive Data
Output
RSYSCLK
Receive System Clock
Input
RSIG
Receive Signaling Output
Output
RLOS/LOTC
Receive Loss of Sync / Loss of Transmit Clock
Output
RCL
Receive Carrier Loss
Output
RSIGF
Receive Signaling Freeze
Output
8MCLK
8 MHz Clock
Output
RPOSO
Receive Positive Data Input
Output
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