DS21552L+ Maxim Integrated Products, DS21552L+ Datasheet - Page 53

• Manufacturer Part Number: DS21552L+
• Description: IC TXRX T1 1-CHIP 5V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21552L+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.3 Multiframes Out Of Sync Count Register (MOSCR)
Normally the MOSCR is used to count the number of multiframes that the receive synchronizer is out of
sync (RCR2.0=1). This number is useful in ESF applications needing to measure the parameters Loss Of
Frame Count (LOFC) and ESF Error Events as described in AT&T publication TR54016. When the
MOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOS=1)
conditions. The MOSCR has alternate operating mode whereby it will count either errors in the Ft
framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the
MOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOS = 1)
conditions. See Table 8-3 for a detailed description of what the MOSCR is capable of counting.
MOSCR1: MULTIFRAMES OUT OF SYNC COUNT REGISTER 1 (Address = 25
Hex) see note 1
MOSCR2: MULTIFRAMES OUT OF SYNC COUNT REGISTER 2 (Address = 27
Hex)
MOS/FB1
NOTES:
1. The lower nibble of the counter at address 25 is used by the Path Code Violation Count Register
2. MOSCR counts either errors in framing bit position (RCR2.0=0) or the number of multiframes out of sync (RCR2.0=1)
Table 8-3 MULTIFRAMES OUT OF SYNC COUNTING ARRANGEMENTS
CRC/FB7
MOS/FB11
(MSB)
SYMBOL
MOS/FB0
1
FRAMING MODE
(CCR2.3)
MOS/FB1
CRC/FB6
ESF
ESF
D4
D4
0
POSITION
MOSCR1.7
MOSCR2.0
MOS/FB9
CRC/FB5
NAME AND DESCRIPTION
MSB of the 12–Bit Multiframes Out of Sync or F–Bit Error Count (note #2)
LSB of the 12–Bit Multiframes Out of Sync or F–Bit Error Count (note #2)
COUNT MOS OR F–BIT
MOS/FB8
CRC/FB4
ERRORS
(RCR2.0)
F–Bit
F–Bit
MOS
MOS
CRC/FB3
(note 1)
53 of 137
CRC/FB2
(note 1)
number of multiframes out of sync
errors in the Ft pattern
number of multiframes out of sync
errors in the FPS pattern
CRC/FB1
(note 1)
WHAT IS COUNTED
IN THE MOSCRs
CRC/FB0
(note 1)
(LSB)
DS21352/DS21552
MOSCR1
MOSCR2