PEB 3086 H V1.4 Infineon Technologies, PEB 3086 H V1.4 Datasheet - Page 191

• Manufacturer Part Number: PEB 3086 H V1.4
• Description: IC ISDN ACCESS CTRLR TQFP64
• Manufacturer: Infineon Technologies
• Series: ISAC™r

Specifications of PEB 3086 H V1.4

• Function: Subscriber Access Controller
• Interface: HDLC, IOM-2, ISDN, Parallel, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Includes: D-Channel Access Control and Priority Handler, Monitor Channel Handler, Non-Auto Mode, Transparent Mode
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB3086HV1.4X; PEB3086HV14XP; SP000007567

A5SEL ... AUX5 Function Select
0: pin AUX5 provides normal I/O functionality.
1: pin AUX5 provides an FSC or BCL signal output (FBOUT) which is selected in
ACFG2.FBS. Bit AOE.OE5 is don’t care, the output characteristic (push pull or open
drain) can be selected via ACFG1.OD5.
For general information please refer to
FBS ... FSC/BCL Output Select
0: FSC is output on pin AUX5.
1: BCL (single bit clock) is output on pin AUX5.
Note: This selection has only effect on pin AUX5 if FBOUT is enabled (A5SEL=1).
For general information please refer to
A4SEL ... AUX4 Function Select
0: pin AUX4 provides normal I/O functionality.
1: pin AUX4 supports multiframe synchronization and is used as M-bit input in Int. NT/
NT/LT-S modes or as M-bit output in TE/LT-T modes (input/output is automatically
selected with the mode). Bit AOE.OE4 is don’t care, the output characteristic (push pull
or open drain) can be selected via ACFG1.OD4.
For general information please refer to
ACL ... ACL Function Select
0: Pin ACL automatically indicates the S-bus activation status by a LOW level.
1: The output state of ACL is programmable by the host in bit LED.
Note: An LED with preresistance may directly be connected to ACL.
LED ... LED Control
If enabled (ACL=1) the LED with preresistance connected between VDD and ACL is
switched ...
0: Off (high level on pin ACL)
1: On (low level on pin ACL)
EL0, 1 ... Edge/Level Triggered Interrupt Input for INT0, INT1
0: A negative level ...
1: A negative edge ... on INT0/1 (pins AUX6/7) generates an interrupt to the ISAC-SX.
Data Sheet
In LT-T mode pin SCLK provides an 1.536 MHz output clock which can be used
as DCL input. This is necessary for BCL generation.
Chapter
Chapter
Chapter
191
3.4.
3.4.
3.3.3.
Detailed Register Description
PEB 3086
2003-01-30
ISAC-SX