PEB 3086 H V1.4 Infineon Technologies, PEB 3086 H V1.4 Datasheet - Page 9

• Manufacturer Part Number: PEB 3086 H V1.4
• Description: IC ISDN ACCESS CTRLR TQFP64
• Manufacturer: Infineon Technologies
• Series: ISAC™r

Specifications of PEB 3086 H V1.4

• Function: Subscriber Access Controller
• Interface: HDLC, IOM-2, ISDN, Parallel, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Includes: D-Channel Access Control and Priority Handler, Monitor Channel Handler, Non-Auto Mode, Transparent Mode
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB3086HV1.4X; PEB3086HV14XP; SP000007567

List of Figures
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Data Sheet
Logic Symbol of the ISAC-SX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Applications of the ISAC-SX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pin Configuration of the ISAC-SX . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Functional Block Diagram of the ISAC-SX. . . . . . . . . . . . . . . . . . . . . . 31
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Direct/Indirect Register Address Mode . . . . . . . . . . . . . . . . . . . . . . . . 38
Interrupt Status and Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Timer Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Timer 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
ACL Indication of Activated Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
ACL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Wiring Configurations in User Premises . . . . . . . . . . . . . . . . . . . . . . . 47
S/T -Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . . 49
Multiframe Synchronization Using the M-Bit . . . . . . . . . . . . . . . . . . . . 52
Sampling Time in LT-S / NT mode (M-Bit input) . . . . . . . . . . . . . . . . . 53
Frame Relationship in LT-S / NT mode (M-Bit input) . . . . . . . . . . . . . . 53
Frame Relationship in TE / LT-T mode (M-Bit output) . . . . . . . . . . . . . 54
Data Delay between IOM-2 and S/T Interface (TE mode only) . . . . . . 55
Data Delay between IOM-2 and S/T Interface with S/G Bit Evaluation
(TE mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Data Delay between IOM-2 and S/T Interface with 8 IOM Channels
(LT-S/NT mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Data Delay between IOM-2 and S/T Interface with 3 IOM Channels
and Maximum Receive Delay(LT-S/NT mode only). . . . . . . . . . . . . . . 57
Equivalent Internal Circuit of the Transmitter Stage . . . . . . . . . . . . . . 58
Equivalent Internal Circuit of the Receiver Stage . . . . . . . . . . . . . . . . 59
Connection of Line Transformers and Power Supply to the ISAC-SX . 60
External Circuitry for Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . . 62
External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . . 63
Disabling of S/T Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
External Loop at the S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Clock System of the ISAC-SX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Phase Relationships of ISAC-SX Clock Signals . . . . . . . . . . . . . . . . . 69
Buffered Oscillator Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Layer-1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
State Transition Diagram (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . 74
9
PEB 3086
2003-01-30
ISAC-SX
Page