PEB 3086 H V1.4 Infineon Technologies, PEB 3086 H V1.4 Datasheet - Page 204

• Manufacturer Part Number: PEB 3086 H V1.4
• Description: IC ISDN ACCESS CTRLR TQFP64
• Manufacturer: Infineon Technologies
• Series: ISAC™r

Specifications of PEB 3086 H V1.4

• Function: Subscriber Access Controller
• Interface: HDLC, IOM-2, ISDN, Parallel, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Includes: D-Channel Access Control and Priority Handler, Monitor Channel Handler, Non-Auto Mode, Transparent Mode
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB3086HV1.4X; PEB3086HV14XP; SP000007567

ISAC-SX
PEB 3086
Detailed Register Description
EN_BCL ... Enable Bit Clock BCL/SCLK
0: The BCL/SCLK clock is disabled
1: The BCL/SCLK clock is enabled.
CLKM ... Clock Mode
If the transceiver is disabled (DIS_TR = ’1’) or in NT, LT-S and Int. NT mode the DCL
from the IOM-2 interface is an input.
0: A double bit clock is connected to DCL
1: A single bit clock is connected to DCL
For general information please refer to
Chapter
3.7.
DIS_OD ... Disable Open Drain Drivers
0: DU/DD are open drain drivers
1: DU/DD are push pull drivers
DIS_IOM ... Disable IOM
DIS_IOM should be set to ’1’ if external devices connected to the IOM interface should
be “disconnected“ e.g. for power saving purposes or for not disturbing the internal IOM
connection between layer 1 and layer 2. However, the ISAC-SX internal operation
between S-transceiver, B-channel and D-channel controller is independent of the
DIS_IOM bit.
0: The IOM interface is enabled
1: The IOM interface is disabled. The FSC, DCL clock outputs have high impedance;
clock inputs are active; DU, DD data line inputs are switched off and outputs have high
impedance; except in TE/LT-T mode the DU line is input (’0’-level causes activation), so
the DU pin must be terminated (pull up resistor).
Data Sheet
204
2003-01-30