PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 53

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

•
– In Sleep mode, the analog information is fed to an analog comparator integrated
– In Power Down mode, the SLICOFI-2x converts the analog information to a digital
In applications using ground start signaling, DuSLIC can be set to the ground start mode.
In this mode, the Tip wire is switched to high impedance mode. Ring ground detection is
performed by the internal current sensor in the SLIC and is transferred to the SLICOFI-2x
via the IT pin.
Ground Key Detection
The scaled longitudinal current information is transferred from the SLIC via the IL pin and
the external resistor
value. For the specified
threshold corresponds to 17 mA (positive and negative). After further post-processing,
this information generates an interrupt (GNDK bit in the INTREG1 register) and ground
key detection is indicated.
The polarity of the longitudinal current is indicated by the GNKP bit in the INTREG1
register. Each change of the GNKP bit generates an interrupt. Both bits (GNDK, GNKP)
can be masked in the MASK register.
The post-processing is performed to guarantee ground key detection, even if
longitudinal AC currents with frequencies of 16
time delay between triggering the ground key function and registering the ground key
interrupt will be less than 40 ms in most cases (
For longitudinal DC signals, the blocking period can be programmed by the Data
Upstream Persistence Counter end value (DUP) in register IOCTL3. DC signals with less
duration will not be detected. The DUP time is equivalent to the half of the cycle time for
the lowest frequency for AC suppression (for values see register IOCTL3 on
In Power Down mode, the SLIC’s internal current sensors are switched off and ground
key detection is disabled.
Preliminary Data Sheet
within the SLICOFI-2x that directly indicates off-hook.
value. It is then filtered and processed further to effectively suppress line
disturbances. If the result exceeds a programmable threshold, an interrupt is
generated to indicate off-hook detection.
In Sleep/Power Down mode (PDRx), a similar mechanism is used. In this mode, the
internal current sensor of the SLIC is switched off to minimize power consumption.
The loop current is therefore fed and sensed through 5 k resistors integrated within
the SLIC. The information is made available on the IT pin and is interpreted by the
SLICOFI-2x.
R
IL
to SLICOFI-2x. This voltage is compared with a fixed threshold
R
IL
(1.6 k , see application circuit
53
2
f
/
3
= 50 Hz, 60 Hz).
, 50 or 60 Hz are superimposed. The
Figure
Functional Description
90,
DS3, 2003-07-11
Page
Page
DuSLIC
353) this
166).