PEB 4364 T V1.2 Infineon Technologies, PEB 4364 T V1.2 Datasheet - Page 84

• Manufacturer Part Number: PEB 4364 T V1.2
• Description: IC SLIC VOICE ACCESS PDSO-36
• Manufacturer: Infineon Technologies
• Series: DuSLICr

Specifications of PEB 4364 T V1.2

• Function: Dual Channel Subscriber Line Interface Circuit (DuSLIC)
• Interface: IOM-2, PCM
• Number Of Circuits: 2
• Voltage - Supply: 3.3 V ~ 5 V
• Current - Supply: 105mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-PDSO
• Includes: DTMF Generator and Decoder, Line Echo Cancellation (LEC), Teletax (TTX) Generation, Universal Tone Detection (UTD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB4364TV1.2XT; SP000007728

3.5
3.5.1
A reset of the DuSLIC is initiated by a power-on reset or by a hardware reset. Hardware
reset requires setting the signal at RESET input pin to low level for at least 4 µs. The
reset input pin has a spike rejection that will safely suppress spikes with a duration of
less than 1 µs.
Note: Maximum spike rejection time is t
The SLICOFI-2x is reset by taking the RESET line to low (see
time:
•
•
•
•
•
With the high going reset signal, the following actions take place:
•
•
•
•
The internal reset routine will then initialize the entire chip to default condition as
described in the SOP default register setting (see
reset routine, it is necessary that all external clocks are supplied. The clocks are
determined by the mode:
•
•
Note: Without valid and stable external clock signals, the DuSLIC will not complete the
The internal reset routine requires 12 frames (12 × 125 µs = 1.5 ms) to be finished
(including PLL start up and clock synchronization) and requires setting the default values
given in
the internal reset routine is finished.
Preliminary Data Sheet
all I/O pins are deactivated
all outputs are inactive (e.g. DXA/DXB)
internal PLL is stopped
internal clocks are deactivated
the chip enters the power down high impedance mode (PDH) when the Reset is 1
(otherwise the chip is in a kind of Reset Mode that does not exactly equal the power
down high impedance mode as the VCM voltage for the SLIC is missing)
Clock detection
PLL synchronization
Reset routine runs
when the reset routine has finished the chip is in power down impedance mode
(PDH)
µC/PCM mode: FSC, MCLK, PCLK
IOM-2 mode: FSC and DCL.
reset sequence properly.
Table
Reset Mode and Reset Behavior
Hardware and Power On Reset
17. The first register access to the SLICOFI-2x may be performed after
rej, max
84
. Minimum spike rejection time is t
Chapter
5). To run through the internal
Operational Description
Figure
36). During this
DS3, 2003-07-11
DuSLIC
rej,min
.