SC16C2552BIA44,529 NXP Semiconductors, SC16C2552BIA44,529 Datasheet - Page 20

• Manufacturer Part Number: SC16C2552BIA44,529
• Description: IC UART DUAL W/FIFO 44-PLCC
• Manufacturer: NXP Semiconductors
• Type: Dual UART with 16-byte FIFOsr

Specifications of SC16C2552BIA44,529

• Number Of Channels: 2, DUART
• Package / Case: 44-LCC (J-Lead)
• Features: 2 Channels
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 4.5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3646-5; 935274408529; SC16C2552BIA44-S

NXP Semiconductors
SC16C2552B_3
Product data sheet
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the modem or
other peripheral device to which the SC16C2552B is connected. Four bits of this register
are used to indicate the changed information. These bits are set to a logic 1 whenever a
control input from the modem changes state. These bits are set to a logic 0 whenever the
CPU reads this register.
Table 18.
[1]
Bit
7
6
5
4
3
2
1
0
Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.
Symbol
MSR[7]
MSR[6]
MSR[5]
MSR[4]
MSR[3]
MSR[2]
MSR[1]
MSR[0]
Modem Status Register bits description
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Description
Carrier Detect, CD. During normal operation, this bit is the complement of the
CD input. Reading this bit in the Loopback mode produces the state of
MCR[3] (OP2A/OP2B).
Ring Indicator, RI. During normal operation, this bit is the complement of the
RI input. Reading this bit in the Loopback mode produces the state of
MCR[2] (OP1A/OP2A).
Data Set Ready, DSR. During normal operation, this bit is the complement of
the DSR input. During the Loopback mode, this bit is equivalent to MCR[0]
(DTR).
Clear To Send, CTS. During normal operation, this bit is the complement of
the CTS input. During the Loopback mode, this bit is equivalent to MCR[1]
(RTS).
CD
RI
DSR
CTS
Rev. 03 — 12 February 2009
logic 0 = no CD change (normal default condition)
logic 1 = the CD input to the SC16C2552B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
logic 0 = no RI change (normal default condition)
logic 1 = the RI input to the SC16C2552B has changed from a logic 0 to a
logic 1. A modem Status Interrupt will be generated.
logic 0 = no DSR change (normal default condition)
logic 1 = the DSR input to the SC16C2552B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
logic 0 = no CTS change (normal default condition)
logic 1 = the CTS input to the SC16C2552B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
[1]
[1]
[1]
[1]
SC16C2552B
© NXP B.V. 2009. All rights reserved.
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