SC68C752BIB48,157 NXP Semiconductors, SC68C752BIB48,157 Datasheet - Page 35
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SC68C752BIB48,157
Manufacturer Part Number
SC68C752BIB48,157
Description
IC UART DUAL 48LQFP
Manufacturer
NXP Semiconductors
Datasheet
1.SC68C752BIBS128.pdf
(48 pages)
Specifications of SC68C752BIB48,157
Number Of Channels
2, DUART
Package / Case
48-LQFP
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
5 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.25 V
Supply Current
4.5 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V or 3.3 V or 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935278767157
SC68C752BIB48
SC68C752BIB48
SC68C752BIB48
SC68C752BIB48
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC68C752BIB48,157
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
11. Dynamic characteristics
Table 27.
T
[1]
[2]
[3]
[4]
SC68C752B_4
Product data sheet
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
d1
d2
d3
d4
d6
d7
d8
d9
d10
d11
d12
d13
d14
d15
d16
d17
d18
h2
h3
h4
WL
WH
XTAL1
(RESET)
su1
su2
w1
amb
RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
Applies to external clock; crystal oscillator max 24 MHz.
Maximum frequency =
Reset pulse must occur when CS is inactive.
=
−
40
Parameter
R/W to chip select
read cycle delay
delay from CS to data
data disable time
write cycle delay
delay from WRITE to output
delay to set interrupt from modem
input
delay to reset interrupt from READ
delay from stop to set interrupt
delay from READ to reset interrupt
delay from start to set interrupt
delay from WRITE to transmit start
delay from WRITE to reset interrupt
delay from stop to set RXRDY
delay from READ to reset RXRDY
delay from WRITE to set TXRDY
delay from start to reset TXRDY
R/W hold time from CS
data hold time
address hold time
pulse width LOW
pulse width HIGH
frequency on pin XTAL1
RESET pulse width
address setup time
data setup time
CS strobe width
°
Dynamic characteristics
C to +85
°
C; tolerance of V
-------------- -
t
w clk
(
1
)
CC
±
10 %, unless specified otherwise.
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 04 — 20 January 2010
Conditions
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
[2][3]
[4]
8T
Min
RCLK
200
10
20
25
10
15
15
10
10
10
16
77
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
CC
[1]
= 2.5 V
24T
16T
1T
1T
Max
100
100
100
RCLK
100
100
100
RCLK
100
100
77
15
RCLK
RCLK
48
-
-
-
-
-
-
-
-
-
-
-
-
[1]
[1]
[1]
[1]
8T
V
SC68C752B
CC
Min
RCLK
200
10
20
25
10
15
15
10
16
30
6
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
= 3.3 V and 5 V
[1]
© NXP B.V. 2010. All rights reserved.
24T
16T
1T
1T
Max
RCLK
RCLK
100
33
70
26
15
24
24
29
RCLK
75
70
RCLK
80
-
-
-
-
-
-
-
-
-
-
-
-
[1]
[1]
[1]
[1]
35 of 48
Unit
ns
ns
ns
ns
ns
ns
s
ns
ns
s
ns
s
ns
ns
s
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns