SC28L202A1DGG/G:11 NXP Semiconductors, SC28L202A1DGG/G:11 Datasheet - Page 21

• Manufacturer Part Number: SC28L202A1DGG/G:11
• Description: IC UART DUAL W/FIFO 56-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L202A1DGG/G:11

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279792112; SC28L202A1DGG/G; SC28L202A1DGG/G

Philips Semiconductors
Global Registers
The ‘Global Registers’, 10 in all, are driven by the interrupt system.
They are defined by the content of the CIR (Current Interrupt
Register) as a result of an interrupt arbitration. In other words they
are indirect registers pointed to by the content of the CIR. The list of
global register follows:
A read of the GRxFIFO will give the content of the RxFIFO that
presently has the highest bid value. The purpose of this system is to
enhance the efficiency of the interrupt system. The global registers
and the CIR update procedure are further described in the Interrupt
Arbitration system
Polling, (Normal and using the CIR)
The ‘arbitrating interrupt system’ will reduce the polling overhead to
only two bus cycles. It only requires an update CIR command and a
CIR read to find if service is needed, and if needed to show what
needs to be serviced.
Many users prefer polled to interrupt driven service where there are
not a large number of fast data channels and/or the host CPU’s
other interrupt overhead is low. The Dual UART is functional in this
environment.
The most efficient method of polling is the use of the ‘update CIR’
command (with the interrupt threshold set to zero) followed by a
read of the CIR. This dummy write cycle will perform the same CIR
capture function that an IACKN falling edge would accomplish in an
interrupt driven system. A subsequent read of the CIR, at the same
address, will give information about an interrupt, if any. If the CIR
type field contains 0s, no interrupt is awaiting service. If the value is
non-zero, the fields of the CIR may be decoded for type; channel
and character count information. Optionally, the global interrupt
registers may be read for particular information about the interrupt
status or use of the global RxD and TxD registers for data transfer
as appropriate. The interrupt context will remain in the CIR until
another update CIR command or an IACKN cycle is initiated by the
host CPU occurs. The CIR loads with x’00 if Update CIR is asserted
when the arbitration circuit has NOT detected an arbitration value
that exceeds the threshold value of the ICR. The global registers
and CIR may be used as ‘vectors’ to the service type required.
Traditional methods of polling status registers may also be used.
Their lower efficiency may be greatly offset by use of the UCIR
command and the read of the CIR. They reduce the many reads and
tests of status registers to only one read and one write. This would
normally be accomplished by setting the interrupt threshold to zero.
Then the moment any system within the DUART needs service the
next poll of the CIR would return a non zero value and the type field
will inform the processor which of the possible 18 systems needs
service. In the case of the FIFOs the number of bytes to be written
or read is also available.
Character and Address Recognition
(Also used for Multi-drop, Xon/Xoff systems)
Character recognition is specific to each of the two UARTs. Three
programmable characters are provided for the character recognition
for each channel. The three are general purpose in nature and may
be set to only cause an interrupt or to initiate some rather complex
2005 Nov 01
GIBCR
GICR
GITR
GRxFIFO Pointer to the interrupting receiver FIFO
GTxFIFO
Dual UART
The byte count of the interrupting FIFO
Channel number of the interrupting channel
Type identification of interrupting channel
Pointer to the interrupting transmitter FIFO
15
operations specific to ‘Multi-drop’ address recognition or in-band
Xon/Xoff flow control.
Character recognition system continually examines the incoming
data stream. Upon the recognition of a character bits appropriate for
the character recognized are set in the Xon/Xoff Interrupt Status
Register (XISR) and in the Interrupt Status Register (ISR). The
setting of these bit(s) will initiate any of the automatic sequences or
and/or an interrupt that may have enabled via the MR3 register.
NOTE: Reading the XISR Clears the status bits associated with the
recognition.
The characters of the recognition system are fully programmable.
The Xon/Xoff characters will be set to the standard characters if the
hardware or software reset is used.
The character recognition circuits are basically designed to provide
general-purpose character recognition. Additional control logic has
been added to allow for Xon/Xoff flow control and for recognition of
the address character in the multi-drop or ‘wake-up’ mode. This logic
also allows for the generation of interrupts in either the
general-purpose recognition mode or the specific conditions
mentioned above.
The generality of the above provides a modicum of compatibility to
BOP (Bit Oriented Protocol) where the generation and detection of
‘flags’ is required. Parts of usually synchronous BOP protocols
(HDLC in particular) are beginning to show up in asynchronous
formats.
Character Stripping
The MR0[7:6] register provides for stripping the characters used for
character recognition. Recall that the character recognition may be
conditioned to control several aspects of the communication.
However this system is first a character recognition system. The
status of the various states of this system is reported in the XISR
and ISR registers. The character stripping of this system allows for
the removal of the specified control characters from the data stream:
two for the Xon /Xoff and one for the wake up. Via control in the
MR0[7:6] register these characters may be discarded (stripped) from
the data stream when the recognition system ‘sees’ them or they
may be sent on the RxFIFO. Whether they are stripped or not the
recognition system will process them according to the action
requested; flow control, wake up, interrupt generation, etc. Care
should be exercised in programming the stripping option if noisy
environments are encountered. If a normal character were corrupted
to a Xoff character the transmitter would be stopped. If that
character were now stripped from the FIFO stack, then that stripping
action would make it difficult to determine the cause of transmitter
stopping.
When character stripping is invoked and a recognition character is
received that has an error bit set that character is sent to the
RxFIFO even though character stripping is active.
Flow Control (Xon/Xoff)
This section describes in-band flow control or Xon/Xoff signaling.
For the RTS/CTS hardware (out-of-band) control see MR1(7) and
MR2(4) descriptions.
The flow control is accomplished via the character recognition
system giving recognition information to the flow control processor.
Xon and Xoff are special characters used by a receiver to start and
stop the remote transmitter that is sending it data. As described
below several modes of manual and automatic flow control are
available by program control.
SC28L202
Product data sheet