SC28L202A1DGG/G:11 NXP Semiconductors, SC28L202A1DGG/G:11 Datasheet - Page 41

• Manufacturer Part Number: SC28L202A1DGG/G:11
• Description: IC UART DUAL W/FIFO 56-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L202A1DGG/G:11

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279792112; SC28L202A1DGG/G; SC28L202A1DGG/G

Philips Semiconductors
IVR – Interrupt Vector Register
The IVR contains the byte that will be placed on the data bus during an IACKN cycle when the GCCR bits (2:1) are set to binary ‘01’. This is the
unmodified form of the interrupt vector.
Modification of the IVR
The table above indicates how the IVR may be modified by the interrupting source. The modification of the IVR as it is presented to the data bus
during an IACK cycle is controlled by the setting of the bits (2:1) in the GCCR (Global Chip Configuration Register).
GICR – Global Interrupting Channel Register
A register associated with the interrupting channel as defined in the CIR. It contains the channel number for the interrupting channel.
GIBCR – Global Interrupting Byte Count Register
A register associated with the interrupting channel as defined in the
CIR. Its numerical value equals TxEL or RxFL at the time IACKN or
‘Update CIR’ command was issued . The true number of bytes
GITR – Global Interrupting Type Register
A register associated with the interrupting channel as defined in the CIR. It contains the type of interrupt code for all interrupts.
GRxFIFO – Global RxFIFO Register
The RxFIFO of the channel indicated in the CIR channel field. Undefined when the CIR interrupt context is not a receiver interrupt. Global
TxFIFO Register
GTxFIFO – Global TxFIFO Register
The TxFIFO of the channel indicated in the CIR channel field. Undefined when the CIR interrupt context is not a transmitter interrupt. Writing to
the GTxFIFO when the current interrupt is not a transmitter event may result in the characters being transmitted on a different channel than
intended.
2005 Nov 01
Bit 7:6
Receiver Interrupt
0x = not receiver
10 = with receive errors
11 = w/o receive errors
Dual UART
Bits 7:0
8 data bits of RxFIFO. MSBs set to 0 for 7, 6, 5 bit data
Bits 7:0
8 data bits of TxFIFO. MSBs not used for 7, 6, 5 bit data
Bits 7:0
8 data bits of the Interrupt Vector (IVR)
Bits 7:3
Always contains bits (7:3) of the IVR
Bits 7:1
Reserved
Bits 7:0
Channel byte count code
00000001 = 1
00000010 = 2
.
11111111 = 255
00000000 = 256
Bit 5
Transmitter Interrupt
0 = not transmitter
1 = transmitter interrupt
Bits 2:1
Will be replaced with current interrupt
type if IVC field of GCCR = 3
Bit 4:3
Reserved
read 0x00
Bit 0
Channel code
0 = a
1 = b
35
Bit 2:0
Other types
000 = not ‘other’ type
001 = Change of State
010 = Address Recognition Event
011 = Xon/Xoff status
ready for transfer to the transmitter or transfer from the receiver. It is
undefined for other types of interrupts
Bit 0
Replaced with interrupting channel
number if IVC field of GCCR > 1
100 = Rx Watchdog
101 = Break Change
110 = Counter Timer
111 = Rx Loop Back Error
SC28L202
Product data sheet