SC28L202A1DGG/G:11 NXP Semiconductors, SC28L202A1DGG/G:11 Datasheet - Page 63

• Manufacturer Part Number: SC28L202A1DGG/G:11
• Description: IC UART DUAL W/FIFO 56-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L202A1DGG/G:11

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279792112; SC28L202A1DGG/G; SC28L202A1DGG/G

1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of
3. Test conditions for outputs: C
4. Typical values are at +25 C, typical supply voltages, and typical processing parameters.
5. Timing is illustrated and referenced to the WRN and RDN inputs. Also, CEN may be the ‘strobing’ input. CEN and RDN (also CEN and
6. Guaranteed by characterization of sample units.
7. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
8. Minimum frequencies are not tested but are guaranteed by design.
9. Clocks for 1X mode should be reasonably symmetrical.
10. Data is usually set up with respect to CEN going LOW—the leading edge of CEN. This mode strongly implies the use of DACKN. (Its use is
Philips Semiconductors
NOTES:
2005 Nov 01
Symbol
68000 or Motorola bus timing (See Figures 7, 8, 9)
t
t
t
t
t
t
t
t
t
t
t
CS(mot)
DS(mot)
DH(mot)
AS(mot)
AH(mot)
DD(mot)
RWD(mot)
DCR
DCW
DAT
CSC
Dual UART
5 ns maximum. For X1/SCLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input voltages of 0.8 V and
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.
be negated for t
not strictly required.) DACKN is derived from the X1/SCLK input. It is seldom that the system clocks that ultimately drive the CEN, address
and RWN signals are synchronous to the X1/SCLK. If address, data, RWN are set up before CEN goes LOW and hold through DACKN, the
timing parameters above will be guaranteed.
Parameter
RWN set-up time to CEN LOW
Data bus set-up time before X1 HIGH
Data hold time after CEN HIGH
Address set-up time to CEN LOW
Address hold time from CEN LOW
Data valid after CEN LOW
HIGH time between read and/or write cycles
DACKN LOW (read cycle) from X1 HIGH
DACKN LOW (write cycle) from X1 HIGH
DACKN high impedance from CEN or IACKN HIGH
CEN or IACKN set–up time to X1 HIGH for minimum DACKN cycle
RWD
time to guarantee that any status register changes are valid.
L
= 85 pF, except interrupt outputs. Test conditions for interrupt outputs: C
10
5, 7
57
LIMITS
Min
5
10
0
10
10
–
10
–
–
–
10
L
= 85 pF, R
4
Typ
–
–
–
–
–
–
–
–
–
–
–
L
= 2.7 k to V
SC28L202
Max
–
–
–
–
–
35
–
35
25
15
–
Product data sheet
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
CC
.