IS82C50A-5 Intersil, IS82C50A-5 Datasheet
IS82C50A-5
Specifications of IS82C50A-5
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IS82C50A-5 Summary of contents
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... CS82C50A-5Z (Note) IS82C50A-5 IS82C50A-5 IS82C50A-5Z IS82C50A-5Z (Note) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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Functional Diagram MICROPROCESSOR INTERFACE CSO 12 CS1 13 CS2 14 ADS DISTR 22 DISTR 21 DOSTR 19 DOSTR ...
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Pinout BAUDOUT 3 82C50A 82C50A (PDIP) TOP VIEW RCLK 9 32 SIN 10 31 SOUT 11 ...
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Pin Description PIN SYMBOL NUMBER TYPE DISTR DISTR 21 I DOSTR DOSTR 18 I D0-D7 1-8 I/O A0, A1, 28, 27 XTAL1 XTAL2 17 O SOUT 11 O GND 20 ...
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Pin Description (Continued) PIN SYMBOL NUMBER TYPE OUT1 34 O OUT2 DCD lNTRPT 30 O SIN CS0, CS1, 12,13, I CS2 ...
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Block Diagram ( DATA BUS BUFFER (40) +5V POWER (20) SUPPLY GND (28) A0 (27) A1 (26) A2 (12) CS0 (13) SELECT CS1 & (14) CONTROL CS2 (25) LOGIC ADS (35) MR (22) DISTR (21) ...
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Accessible Registers The three types of internal registers in the 82C50A used in the operation of the device are control, status, and data registers. The control registers are the Bit Rate Select Register DLL and DLM, Line Control Register, Interrupt ...
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LINE CONTROL REGISTER (LCR) The format of the data character is controlled by the Line Control Register. The contents of the LCR may be read, eliminating the need for separate storage of the line characteristics in system memory. The contents ...
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LSR BITS 0 THRU 7 LSR (0) Data Ready (DR) LSR (1) Overrun Error (OE) LSR (2) Parity Error (PE) LSR (3) Framing Error (FE) LSR (4) Break Interrupt (BI) LSR (5) Transmitter Holding Register Empty (THRE) LSR (6) Transmitter ...
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MCR(3): When MCR(3) is set high, the OUT2 output is forced low. When MCR(3) is reset low, the OUT2 output is forced high. OUT2 is an user designated output. MCR(4): MCR(4) provides a local loopback feature for diagnostic testing of ...
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MSR(3) Delta Data Carrier Detect (DDCD): DDCD indicates that the DCD input (Pin-36) to the 82C50A has changed state since the last time it was read by the CPU. MSR(4) Clear to Send (CTS): Clear to Send (CTS) is the ...
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RBR before complete reception of the next character result in the loss of the data in the Receiver Register. The OE flag in the LSR register indicates the overrun condition. RBR Bits 0 thru 7 RBR (0) ...
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INTERRUPT ENABLE REGISTER (IER) The Interrupt Enable Register (IER Write register used to independently enable the four 82C50A interrupts which activate the interrupt (lNTRPT) output. All interrupts are disabled by resetting IER(0) - IER(3) of the Interrupt Enable ...
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Transmitter The serial transmitter section consists of a Transmitter Holding Register (THR), Transmitter Shift Register (TSR), and associated control logic. The Transmitter Holding Register Empty (THRE) and Transmitter Shift Register Empty (TEMT) are two bits in the Line Status Register ...
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TABLE 5. BAUD RATES USING 2.4576MHz CRYSTAL DESIRED DIVISOR USED TO BAUD GENERATE DIFFERENCE BETWEEN RATE 16 x CLOCK DESIRED AND ACTUAL 50 3072 75 2048 110 1396 134.5 1142 150 1024 300 512 600 256 1200 128 1800 85 ...
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Programming The 82C50A is programmed by the control registers LCR, lER, DLL and DLM, and MCR. These control words define the character length, number of stop bits, parity, baud rate, and modem interface. While the control registers can be written ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Specifications V Timing Requirements SYMBOL PARAMETER (1) TAW Address Strobe Width (2) TAS Address Setup Time (3) TAH Address Hold Time (4) TCS Chip Select Setup Time (5) TCH Chip Select Hold Time (6) TDIW DISTR DlSTR Strobe ...
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AC Electrical Specifications V Timing (Continued) SYMBOL PARAMETER BAUD GENERATOR (29) N Baud Divisor (30) TBLD Baud Output Negative Edge Delay (31) TBHD Baud Output Positive Edge Delay (32) TLW Baud Output Down Time (33) THW Baud Output Up Time ...
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AC Test Circuit V1 OUTPUT FROM DEVICE UNDER TEST NOTE: Includes stay and jig capacitance. TEST CONDITION DEFINITION TABLE IOH IOL V1 -2.5mA +2.5mA 1.7V Timing Waveforms tXH (27) XTAL1 tXL (28) FIGURE 3. EXTERNAL CLOCK INPUT XTAL1 (31) tBHD ...
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Timing Waveforms (Continued) ADS (2) tAS A2, A1, A0 (4) tCS CS2, CS1, CS0 CSOUT DOSTR/DOSTR DISTR/DISTR DATA D0-D7 † Applicable only when ADS is tied low. ADS (2) tAS A2, A1, A0 (4) tCS CS2, CS1, CS0 CSOUT DISTR/DISTR ...
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Timing Waveforms (Continued) SAMPLE CLK SIN (RECEIVER INPUT DATA) SAMPLE CLK (DATA READY OR RCVR ERR) DISTR/DISTR (READ REC DATA BUFFER OR ROLSR) NOTES: 1. See Write Cycle Timing. 2. See Read Cycle Timing. SERIAL OUT (SOUT) INTERRUPT (THRE) DOSTR/DOSTR ...
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Timing Waveforms (Continued) DOSTR/DOSTR (WR MCR) OUT1, OUT2 CTS, DST, DCD INTERRUPT DISTR/DISTR (RD MSR) NOTES: 1. See Write Cycle Timing. 2. See Read Cycle Timing. 23 82C50A ACTIVE NOTE 1 tMDO (42) RTS, DTR tRIM (43) tSIM (44) NOTE ...
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Dual-In-Line Plastic Packages (PDIP INDEX N/2 AREA -B- -A- D BASE PLANE -C- SEATING PLANE 0.010 (0.25 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between ...
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