VSC7135QN Vitesse Semiconductor Corp., VSC7135QN Datasheet

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VSC7135QN

Manufacturer Part Number
VSC7135QN
Description
1.25Gbits/sec Gigabit Ethernet Transceiver
Manufacturer
Vitesse Semiconductor Corp.
Datasheet

Specifications of VSC7135QN

Case
QFP
Dc
99+

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VSC7135
Data Sheet
5/28/98
G52146-0, Rev. 4.0
Features
General Description
tions. It accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK and serializes it
onto the TX PECL differential outputs at a baud rate which is ten times the REFCLK frequency. The VSC7135
also samples serial receive data on the RX PECL differential inputs, recovers the clock and data, deserializes it
onto the 10-bit receive data bus, outputs two recovered clocks at one-twentieth of the incoming baud rate and
detects “Comma” characters. The VSC7135 contains on-chip PLL circuitry for synthesis of the baud-rate trans-
mit clock, and extraction of the clock from the received serial stream. These circuits are fully monolithic and
require no external components.
VSC7135 Block Diagram
COM_DET
EN_CDET
The VSC7135 is a 1.25Gb/s Ethernet Transceiver optimized for Gigabit Ethernet or 1000Base-X applica-
REFCLK
• Gigabit Ethernet Transceiver @ 1.25Gb/s
• Compliant to IEEE 802.3Z PMA
• TTL Interface Compatible to PMA-TBI
• Monolithic Clock Synthesis and Clock
• 125MHz TTL Reference Clock
EWRAP
RCLKN
RCLK
Recovery - No External Components
R0:9
T0:9
10
10
Resync
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Q D
Frame
Logic
D Q
VITESSE
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
PLL Clock
Multiply
to Serial
Comma
Parallel
Serial to
Detect
Parallel
10
20
Retimed
Recovered
Data
Clock
Q D
• Low Power Operation - 700 mW
• Suitable for Both Coaxial or Optical Link
• 64 Pin, 14mm or 10mm Standard PQFP
• Single +3.3V Supply
Applications
Synthesized
Serial Data
Clock
Recovery
Clock
Gigabit Ethernet Transceiver
D Q
2:1
1.25Gbits/sec
TX+
TX-
RX+
RX-
Page 1

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VSC7135QN Summary of contents

Page 1

Data Sheet VSC7135 Features • Gigabit Ethernet Transceiver @ 1.25Gb/s • Compliant to IEEE 802.3Z PMA • TTL Interface Compatible to PMA-TBI • Monolithic Clock Synthesis and Clock Recovery - No External Components • 125MHz TTL Reference Clock General Description ...

Page 2

Gigabit Ethernet Transceiver Functional Description Clock Synthesizer The VSC7135 clock synthesizer multiplies the reference frequency provided on the REFCLK pin achieve a baud rate clock at nominally 1.25GHz. The clock synthesizer contains a fully monolithic PLL ...

Page 3

Data Sheet VSC7135 ing parallel data will be captured by the adjoining protocol logic on the rising edges of RCLK and RCLKN. In order to maximize the setup and hold times available at this interface, the parallel data is loaded ...

Page 4

Gigabit Ethernet Transceiver Figure 2: Detection of a Properly Aligned Comma Character RCLK RCLKN COM_DET R0:9 TChar: 10 bit Transmission Character Figure 3: Detection and Resynchronization of an Improperly Aligned Comma Receiving Two Consecutive K28.5+TChar Transmission Words RCLK RCLKN ...

Page 5

Data Sheet VSC7135 AC Characteristics REFCLK T0:9 Data Valid 10 Bit Data Table 1: Transmit AC Characteristics Parameters Description T0:9 Setup time to the rising T 1 edge of REFCLK T0:9 hold time after the T 2 rising edge of ...

Page 6

Gigabit Ethernet Transceiver RCLK RCLKN R0:9 Data Valid Table 2: Receive AC Characteristics Parameters Description Data or COM_DET Valid T prior to RCLK/RCLKN 1 rise Data or COM_DET Valid T after RCLK or RCLKN 2 rise Deviation of RCLK ...

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Data Sheet VSC7135 REFCLK Table 3: Reference Clock Requirements Parameters Description FR Frequency Range FO Frequency Offset DC REFCLK duty cycle T ,T REFCLK rise and fall time RCR RCF REFCLK Jitter Power REFCLK 5 MHz Jitter PhaseNoise 100Hz G52146-0, ...

Page 8

Gigabit Ethernet Transceiver DC Characteristics (Over recommended operating conditions). Parameters Description V Output HIGH voltage (TTL Output LOW voltage (TTL Output differential peak OUT75 to-peak voltage swing TX Output differential peak ...

Page 9

Data Sheet VSC7135 Figure 7: Parametric Measurement Information Serial Input Rise and Fall Time T r Receiver Input Eye Diagram Jitter Tolerance Mask Serial Output Load G52146-0, Rev. 4.0 5/28/98 741 Calle Plano, Camarillo, CA 93012 ...

Page 10

Gigabit Ethernet Transceiver Input Structures INPUT INPUT INPUT Page 10 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION Figure 8: Input Structures V +3 Current Limit R R GND REFCLK and ...

Page 11

Data Sheet VSC7135 Package Pin Descriptions V SSD DDD DDD SSD V SSD N/C (Top View) Table 4: Pin Identification Pin # Name INPUTS - TTL 2-4, ...

Page 12

Gigabit Ethernet Transceiver Pin # Name INPUT - TTL LOW for Normal Operation. When HIGH, an internal loopback path from the 19 EWRAP transmitter to the receiver is enabled and the TX outputs are held HIGH. INPUTS - Differential ...

Page 13

Data Sheet VSC7135 Package Information TYP TYP 0.30 RAD. TYP. 0.20 RAD G52146-0, Rev. 4.0 5/28/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR ...

Page 14

Gigabit Ethernet Transceiver Package Thermal Considerations The VSC7135 is packaged conventional PQFP with an internal heat spreader. This package use an industry-standard EIAJ footprint, but have been enhanced to improve thermal dissipation. The construction of ...

Page 15

Data Sheet VSC7135 Ordering Information The part number for this product is formed by a combination of the device number and the package style: Device Type: VSC7135: 1.25 Gbps Transceiver Package Style (64-pin) QN: 14x14mm PQFP QU: 10x10mm PQFP Marking ...

Page 16

Gigabit Ethernet Transceiver Page 16 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 G52146-0, Rev. 4.0 5/28/98 ...

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