VSC7123QN Vitesse Semiconductor Corp., VSC7123QN Datasheet

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VSC7123QN

Manufacturer Part Number
VSC7123QN
Description
10-bit transceiver for fibre channel and Gigabit ethernet. 3.3V power supply voltage
Manufacturer
Vitesse Semiconductor Corp.
Datasheet

Specifications of VSC7123QN

Case
QFP
Dc
02+

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VSC7123
Data Sheet
G52212-0, Rev 4.3
03/25//01
Features
General Description
pinouts. The VSC7123 accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK
and serializes the data onto the TX PECL differential outputs at a baud rate which is 10 times the REFCLK
frequency. Serial data input on the RX PECL differential inputs is resampled by the Clock Recovery Unit
(CRU) and deserialized onto the 10-bit receive data bus synchronously to complementary divide-by-twenty
clocks. The VSC7123 receiver detects “Comma” characters for frame alignment. An analog/digital signal
detection circuit indicates that a valid signal is present on the RX input. A cable equalizer compensates for
InterSymbol Interference (ISI) in order to increase maximum cable distances. The VSC7123 is a higher
performance, lower cost replacement for the VSC7125 and VSC7135.
VSC7123 Block Diagram
The VSC7123 is a full-speed Fibre Channel and Gigabit Ethernet Transceiver with industry-standard
• 802.3z Gigabit Ethernet-Compliant
• ANSI X3T11 Fibre Channel-Compliant
• 0.98 to 1.36 Gb/s Full-Duplex Operation
• 10-Bit TTL Interface for Transmit and
COMDET
ENCDET
REFCLK
EWRAP
RCLKN
SIGDET
1.25 Gb/s Transceiver
1.0625 Gb/s Transceiver
Receive Data
R(0:9)
T(0:9)
RCLK
10
10
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Q D
VITESSE
SEMICONDUCTOR CORPORATION
Comma
x10 Clock
Detect
Multiply
D Q
Q
Serial to
Parallel
Internet: www.vitesse.com
D
to Serial
Parallel
• Automatic Lock-to-Reference
• RX Cable Equalization
• Analog/Digital Signal Detection
• JTAG Access Port for Testability
• Single +3.3V Supply, 650mW Typical
• Packages: 64-Pin 10mm and 14mm PQFP and
10
20
10mm TQFP
Recovery
Q D
Clock
D Q
NOT SHOWN: JTAG Boundary Scan
Channel and Gigabit Ethernet
2:1
10-Bit Transceiver for Fibre
Detect
Signal
TX+
TX-
RX+
RX-
Page 1

Related parts for VSC7123QN

VSC7123QN Summary of contents

Page 1

Data Sheet VSC7123 Features • 802.3z Gigabit Ethernet-Compliant 1.25 Gb/s Transceiver • ANSI X3T11 Fibre Channel-Compliant 1.0625 Gb/s Transceiver • 0.98 to 1.36 Gb/s Full-Duplex Operation • 10-Bit TTL Interface for Transmit and Receive Data General Description The VSC7123 is ...

Page 2

Transceiver for Fibre Channel and Gigabit Ethernet Functional Description Clock Synthesizer The VSC7123 clock synthesizer multiplies the reference frequency provided on the REFCLK pin achieve a baud rate clock between 0.98GHz and 1.36GHz. The on-chip Phase ...

Page 3

Data Sheet VSC7123 serial data is retimed, deserialized and output on R(0:9). The parallel data will be captured by the adjoining protocol logic on the rising edges of RCLK and RCLKN. If serial input data is not present or does ...

Page 4

Transceiver for Fibre Channel and Gigabit Ethernet Figure 2: Detection of a Properly Aligned Comma Character RCLK RCLKN COMDET R(0:9) RCLK RCLKN COMDET R(0:9) Potentially Corrupted Page 4 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA ...

Page 5

Data Sheet VSC7123 Signal Detection The receiver has an output, SIGDET, indicating, when HIGH, that the RX input contains a valid Fibre Channel or Gigabit Ethernet signal. A combination of one analog and three digital checks are used to determine ...

Page 6

Transceiver for Fibre Channel and Gigabit Ethernet REFCLK T(0:9) Data Valid Table 2: Transmit AC Characteristics Parameters Description T(0:9) Setup time to the rising T 1 edge of REFCLK T(0:9) hold time after the rising T 2 edge of ...

Page 7

Data Sheet VSC7123 RCLK RCLKN Data Valid R(0:9) Table 3: Receive AC Characteristics Parameters Description TTL Outputs Valid prior RCLK/RCLKN rise TTL Outputs Valid after T 2 RCLK or RCLKN rise Delay between rising edge of T ...

Page 8

Transceiver for Fibre Channel and Gigabit Ethernet REFCLK Table 4: Reference Clock Requirements Parameter Description FR Frequency Range FO Frequency Offset DC REFCLK duty cycle T ,T REFCLK rise and fall time R F Page 8 © VITESSE SEMICONDUCTOR ...

Page 9

Data Sheet VSC7123 Figure 7: Parametric Measurement Information Serial Input Rise and Fall Time T R Receiver Input Eye Diagram Jitter Tolerance Mask Serial Output Load Z = 75W 0 G52212-0, Rev 4.3 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle ...

Page 10

Transceiver for Fibre Channel and Gigabit Ethernet V DDD INPUT GND TTL Inputs (not REFCLK +3.3 V 12.6K REFCLK 9.3K 12.6K GND REFCLK TTL Input V DDT V V SST SSD TTL Outputs Page 10 © VITESSE ...

Page 11

Data Sheet VSC7123 DC Characteristics (over recommended operating conditions) Parameters Description V Output HIGH voltage (TTL Output LOW voltage (TTL Input HIGH voltage (TTL Input LOW voltage (TTL Input HIGH current (TTL) ...

Page 12

Transceiver for Fibre Channel and Gigabit Ethernet Absolute Maximum Ratings Power Supply Voltage ................................................................................................................ – 0. Input Voltage (PECL inputs) ................................................................................................ – 0. Input Voltage (TTL inputs) ........................................................................................................... – 0.5V ...

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Data Sheet VSC7123 Package Pin Descriptions 1 V SSD DDD DDD SSD 15 V SSA CAP0 17 Table 5: Pin Identifications ...

Page 14

Transceiver for Fibre Channel and Gigabit Ethernet Pin # Name OUTPUTS - Differential PECL (AC-coupling recommended): 62, 61 TX+, TX- These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is HIGH, TX+ is HIGH and ...

Page 15

Data Sheet VSC7123 Package Information: 64-pin PQFP TYP 0.30 RAD. TYP. 0.20 RAD. TYP. G52212-0, Rev 4.3 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 ...

Page 16

Transceiver for Fibre Channel and Gigabit Ethernet Package Information: 64-pin TQFP 11/13 8 PLACES A 0.08/0.20 R 0.08 R MIN Page 16 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • ...

Page 17

Data Sheet VSC7123 Package Thermal Considerations The VSC7123 is packaged in a 14mm, thermally-enhanced PQFP with an internal heat spreader a 10 mm, thermally enhanced PQFP and a 10mm cavity-down, exposed pad TQFP. These packages use industry-standard EIAJ footprints, but ...

Page 18

Transceiver for Fibre Channel and Gigabit Ethernet Ordering Information The part number for this product is formed by a combination of the device number and the package style. Device Type 10-Bit Transceiver Marking Information The package is marked with ...

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