VSC7217UC Vitesse Semiconductor Corp., VSC7217UC Datasheet

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VSC7217UC

Manufacturer Part Number
VSC7217UC
Description
Milti-gigabit interconnect chip. 3.3V supply, 3.0V typ., 3.3V max
Manufacturer
Vitesse Semiconductor Corp.
Datasheet

Specifications of VSC7217UC

Case
BGA
Dc
00+
VSC7217
6/14/00
Preliminary Datasheet
G52325-0, Rev. 3.0
Features
VSC7217 Block Diagram
REFCLKN
REFCLKP
TD(7:0)
WSEND
WSENC
KCHAR
TC(7:0)
WSENB
WSENA
TB(7:0)
TA(7:0)
DUAL
TBCC
TBCD
C/DD
TBCA
TBCB
C/DC
C/DB
C/DA
• 4 ANSI X3T11 Fibre Channel and IEEE
• Over 8 Gb/s Duplex Raw Data Rate
• Redundant PECL Tx Outputs and Rx Inputs
• 8B/10B Encoder/Decoder per Channel,
• “ASIC-Friendly
• Elastic Buffers for Intra/Inter-Chip Cable
• Tx/Rx Rate Matching via IDLE Insertion/
802.3z Gigabit Ethernet Compliant Trans-
ceivers
Optional Encoder/Decoder Bypass Operation
Transmitter Parallel Input Data
Deskewing and Channel-to-Channel Align-
ment
Deletion
8
8
8
8
D Q
D Q
D Q
D Q
Clock Gen
CAP0 CAP1
x20/x10
4
8
8
8
8
TRANSMITTER
Encode
Encode
Encode
Encode
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
8B/10B
8B/10B
8B/10B
8B/10B
TM
PTXEND
RTXEND
PTXENC
RTXENC
PTXENB
PTXENA
RTXENB
RTXENA
Tx Clock
REFCLK
” Timing Options for
TBERRC
TBERRD
TBERRA
TBERRB
10
10
10
10
VITESSE
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
LBTXD
LBTXC
LBTXB
LBTXA
PTXD+
PTXD-
RTXD+
RTXD-
PTXC+
PTXC-
RTXC+
RTXC-
PTXB+
PTXB-
RTXB+
RTXB-
PTXA+
PTXA-
RTXA+
RTXA-
RMODE(1:0)
TMODE(2:0)
PRXD+
PRXD-
RRXD+
RRXD-
PRXC+
PRXC-
RRXC+
RRXC-
PRXB+
PRXB-
RRXB+
RRXB-
PRXA+
PRXA-
RRXA+
RRXA-
LBEND(1:0)
LBENC(1:0)
LBENB(1:0)
LBENA(1:0)
RXP/RD
RXP/RC
RXP/RB
RXP/RA
• Compatible with VSC7211/7212/7214
• Fast-Locking CRU: 100-Bit Clock Periods
• Received Data Aligned to Local REFCLK or to
• PECL Rx Signal Detect and Cable Equalization
• Per-Channel Serial Tx-to-Rx and Parallel Rx-to-
• Clock Multiplier Generates Baud Rate Clock
• Automatic Lock-to-Reference
• JTAG Boundary Scan Support for TTL I/O
• Built-In Self Test
• 3.3V Supply, 3.0W Typ, 3.5W Max.
• 256-pin, 27mm BGA Package
Recovery
Recovery
Recovery
Recovery
RESETN
Clk/Data
Clk/Data
Clk/Data
Clk/Data
Recovered Clock
Tx Internal Loopback Modes
ENDEC
PSDETC
RSDETC
PSDETD
RSDETD
PSDETB
RSDETB
PSDETA
RSDETA
RECEIVER
BIST
10
10
10
10
Decode
Decode
Decode
Decode
8B/10B
8B/10B
8B/10B
8B/10B
Multi-Gigabit Interconnect Chip
FLOCK
TRSTN
TMS
TDI
WSI
TCK
8
3
8
3
8
3
8
3
Elastic
Elastic
Elastic
Elastic
Buffer
Buffer
Buffer
Buffer
Boundary
Channel
Align
JTAG
Scan
8
8
8
8
RD(7:0)
IDLED
KCHD
ERRD
RC7:0)
IDLEC
KCHC
ERRC
RCLKC
RCLKCN
RB(7:0)
IDLEB
KCHB
ERRB
RCLKB
RCLKBN
RA(7:0)
IDLEA
KCHA
ERRD
RCLKA
RCLKAN
WSO
TDO
RCLKD
RCLKDN
Page 1

Related parts for VSC7217UC

VSC7217UC Summary of contents

Page 1

Preliminary Datasheet VSC7217 Features • 4 ANSI X3T11 Fibre Channel and IEEE 802.3z Gigabit Ethernet Compliant Trans- ceivers • Over 8 Gb/s Duplex Raw Data Rate • Redundant PECL Tx Outputs and Rx Inputs • 8B/10B Encoder/Decoder per Channel, Optional ...

Page 2

Mutli-Gigabit Interconnect Chip General Description The VSC7217 is a quad 8-bit parallel-to-serial and serial-to-parallel transceiver chip used for high band- width interconnection between busses, backplanes, or other subsystems. Four Fibre Channel and Gigabit Ether- net compliant transceivers provide up to ...

Page 3

Preliminary Datasheet VSC7217 Transmitter Functional Description Transmitter Data Bus Each VSC7217 transmit channel has an 8-bit input transmit data character, Tn(7:0), and two control inputs, C/Dn and WSENn. The C/Dn input determines whether a normal data character or a special ...

Page 4

Mutli-Gigabit Interconnect Chip mit data rate that is locked to the selected input timing source. This is an especially important when DUAL is HIGH and input timing is referenced to REFCLK, since the falling edge is NOT used. The internal ...

Page 5

Preliminary Datasheet VSC7217 8B/10B Encoder Each channel contains an 8B/10B encoder which translates the 8-bit input data on Tn(7:0) into a 10-bit encoded data character. C/Dn inputs are also provided in each channel which, along with KCHAR, allow the transmission ...

Page 6

Mutli-Gigabit Interconnect Chip four transmit channel inputs for serialization will be transferred on the receive channel parallel outputs. The Word Sync Sequence provides a unique synchronization point in the serial data stream that is used to align the receive channels. ...

Page 7

Preliminary Datasheet VSC7217 mary or redundant serial input as the data source for that channel. When RXP/RC is HIGH, the C channel serial data source is PRXC. When LBENn(1:0)=10, the channel’s transmitter is looped back and becomes the serial data ...

Page 8

Mutli-Gigabit Interconnect Chip Deserializer and Character Alignment The retimed serial data stream is converted into 10-bit characters by the deserializer. A special 7-bit “Comma” pattern (‘0011111xxx’ or ‘1100000xxx’) is recognized by the receiver and allows it to identify the 10-bit ...

Page 9

Preliminary Datasheet VSC7217 The VSC7217 presents recovered data on Rn(7:0) and status on IDLEn, KCHn and ERRn. These outputs are timed either to each channel’s own recovered clock (RCLKn/RCLKNn), to Channel A’s recovered clock (RCLKA/RCLKNA REFCLK. The output ...

Page 10

Mutli-Gigabit Interconnect Chip REFCLK (DUAL = 0) REFCLK (DUAL = 1) Rn(7:0) IDLEn KCHn ERRn RCLKn (DUAL = 0) RCLKn (DUAL = 1) Rn(7:0) IDLEn KCHn ERRn The data coming from the decoder is clocked into the elastic buffer by ...

Page 11

Preliminary Datasheet VSC7217 The elastic buffer is designed to allow a maximum phase drift serial clock bit times between re- synchronizations, which sets a limit on the maximum data “packet” length allowed between IDLEs. This maxi- ...

Page 12

Mutli-Gigabit Interconnect Chip Word Sync Sequence will be properly word-aligned. In the process of channel alignment, one or two of the final twelve K28.5 characters in the Word Sync Sequence may be deleted or duplicated. This ensures that each trans- ...

Page 13

Preliminary Datasheet VSC7217 If the transmitting devices’ REFCLKs are not frequency locked to the receiving devices’ REFCLKs, IDLEs will have to be added to or dropped from all the channels at the same time. In order to implement this, one ...

Page 14

Mutli-Gigabit Interconnect Chip entered whenever four consecutive invalid transmissions have been detected or when the occurrences of invalid transmission outnumber those of valid transmission by four. The relative occurrences of invalid vs. valid trans- missions are monitored with a simple ...

Page 15

Preliminary Datasheet VSC7217 Link Status Outputs The receiver ERRn, KCHn and IDLEn outputs indicate status for each channel as shown below in Table 7. Since this status is encoded, multiple conditions could occur simultaneously so the states are prioritized as ...

Page 16

Mutli-Gigabit Interconnect Chip Loopback Operation Loopback control pins, LBENn(1:0), are provided in each channel to internally loopback data paths for on- chip diagnosis. Both serial and parallel loopback functions are provided. Table 8: Loopback Mode Selection LBENn(1:0) Loopback Mode 0 ...

Page 17

Preliminary Datasheet VSC7217 Figure 11: Parallel Loopback Mode Operation LBENn(1:0) RXP/Rn LBTXn Clk/Data PRXn+ Recovery PRXn- RRXn+ RRXn- PSDETn RSDETn RECEIVER BIST PTXENn 1 8 Gen 8B/10B Tn(7:0) Encode C/Dn 0 WSENn RTXENn REFCLK 0 1 ...

Page 18

Mutli-Gigabit Interconnect Chip Compatibility with VSC7214 and VSC7211 Care has been taken in the functional definition of the VSC7217 ensure compatiblity with the VSC7211 and VSC7214 at the serial link level, and that the transmitter and receiver low-speed interfaces have ...

Page 19

Preliminary Datasheet VSC7217 VSC7214 MODE 1: RCLKEN=LOW, FLOCK=LOW, INDEP=HIGH Receiver Rn(7:0), ERRn, KCHn and IDLEn outputs are synchronous to REFCLK, IDLE insertion/dele- tion is enabled, and the receive channels are independent. The VSC7217 should be configured with RMODE(1:0)=00, FLOCK=0, and ...

Page 20

Mutli-Gigabit Interconnect Chip AC Specifications Figure 13: Transmit Input Timing Waveforms with TMODE = 000 REFCLK (DUAL=0) REFCLK (DUAL=1) Internal Clock (from PLL) Tn(7:0) C/Dn WSENn Figure 14: Transmit Input Timing Waveforms with TMODE = 10X TBCn (or TBCA) Internal ...

Page 21

Preliminary Datasheet VSC7217 Figure 15: Transmit Input Timing Waveforms with TMODE = 11X (“ASIC-Friendly” Timing) TBCn (or TBCA) Internal Clock (from PLL) Tn(7:0) C/Dn WSENn Table 10: Transmit Input AC Characteristics with TMODE = 11X Parameters Description Input Skew relative ...

Page 22

Mutli-Gigabit Interconnect Chip Figure 17: Receive Output Timing Waveforms with RMODE = REFCLK (DUAL = 0) REFCLK (DUAL = 1) Rn(7:0) TBERRn KCHn IDLEn ERRn PSDETn RSDETn Table 12: Receive Output AC Characteristics with RMODE = 00 ...

Page 23

Preliminary Datasheet VSC7217 Figure 19: RCLKn and RCLKNn Timing Waveforms with DUAL = 1 RCLKn RCLKNn Table 14: General Receive AC Characteristics Parameters Description Delay Between Rising Edge T of RCLKn to Rising Edge 3 of RCLKNn RCLKn to RCLKNn ...

Page 24

Mutli-Gigabit Interconnect Chip REFCLK Table 15: Reference Clock Requirements Parameters Description FR Frequency Range FO Frequency Offset DC REFCLK Duty Cycle T ,T REFLCK and TBC Pulse Width REFCLK Rise and Fall Times RCR RCF REFCLK ...

Page 25

Preliminary Datasheet VSC7217 Figure 21: Parametric Measurement Information Serial Input Rise and Fall Time T r Receiver Input Eye Diagram Jitter Tolerance Mask Serial Output Load G52325-0, Rev. 3.0 6/14/00 741 Calle Plano, Camarillo, CA 93012 ...

Page 26

Mutli-Gigabit Interconnect Chip DC Characteristics Parameters Description TTL Outputs (Rn(7:0), KCHn, IDLEn, ERRn, RCLKn/RCLKNn, TBERRn, PSDETn, RSDETn, WSO) V TTL Output HIGH Voltage OH V TTL Output LOW Voltage OL I TTL Output Leakage Current OZ TTL Inputs (TBCn, Tn(7:0), ...

Page 27

Preliminary Datasheet VSC7217 Absolute Maximum Ratings Power Supply Voltage, (any V PECL Differential Input Voltage............................................................................................ -0. TTL Input Voltage...........................................................................................................................-0.5V to +5.5V TTL Output Voltage .............................................................................................................. -0. TTL Output Current ...................................................................................................................................... 50mA PECL Output Current .................................................................................................................................... 50mA ...

Page 28

Mutli-Gigabit Interconnect Chip Table 16: Pin Table Page 28 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC7217 G52325-0, Rev. 3.0 6/14/00 ...

Page 29

Preliminary Datasheet VSC7217 Table 17: Pin Description Pin Name I/O 6Y, 8U, 7W, 5Y, I 7V, 7U, TA(7:0) 6W, 5W 11U, 11W, 10Y, 10W, I 10U, 10V, TB(7:0) 9Y, 9W 12A, 11C, 11D, 10A, I 10B, 10D, TC(7:0) 10C, 9A ...

Page 30

Mutli-Gigabit Interconnect Chip Pin Name I/O 1R, 2R PTXA+/- 1M, 2M PTXB+/- O 1J, 2J PTXC+/- 1F, 2F PTXD+/- 1T, 2T RTXA+/- 1N, 2N RTXB+/- O 1H, 2H RTXC+/- 1E, 2E RTXD+/- 4N PTXENA 4M PTXENB I 4J PTXENC 4H ...

Page 31

Preliminary Datasheet VSC7217 Pin Name I/O 18N ERRA 16U ERRB O 20A ERRC 20F ERRD 20M RCLKA 19M RCLKNA 17T RCLKB 20Y RCLKNB O 18E RCLKC 17E RCLKNC 17K RCLKD 18K RCLKND 6U RMODE0 I 4W RMODE1 1U, 2U PRXA+/- ...

Page 32

Mutli-Gigabit Interconnect Chip Pin Name I/O 8A REFCLKP I 9D REFCLKN 1K CAP0 1L CAP1 5U DUAL I 13W FLOCK I 12D BIST I 12V ENDEC I 12U RESETN I 20L WSI I 17L WSO O 15A TCK I 13B ...

Page 33

Preliminary Datasheet VSC7217 Pin Name I/O 11A, 13C, 13U, 19L, 3C, 3K, 3V, VSSD 4C, 4E, 4T, 4V, 6V, 7A, 7C, 8W 14B, 14W, 17B, 17D, 17H, 17P, 17U, 17W, VDDT 18L, 19B, 19E, 19G, 19J, 19N, 19T, 19W 14C, ...

Page 34

Mutli-Gigabit Interconnect Chip Package Thermal Considerations The VSC7217 is packaged in a 256-pin, 27mm, thermally enhanced BGA in a 20x20 array which offers excellent electrical characteristics, good thermal performance and small size. This package uses an industry- standard footprint. The ...

Page 35

Preliminary Datasheet VSC7217 Package Information 1.27 Typ 27.0 BOTTOM VIEW G52325-0, Rev. 3.0 6/14/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION 256-pin BGA ...

Page 36

... Vitesse Semiconductor Corporation’s products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. Page 36 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION xx VSC7217 VSC7217UC ####AAAA VITESSE VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC7217 Package UC: 256-Pin, 27mm BGA ...

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