VSC8114QB Vitesse Semiconductor Corp., VSC8114QB Datasheet

VSC8114QB

Manufacturer Part Number

VSC8114QB

Description

ATM/SONET/SDH 622 Mb/s transceiver Mux/Demux with integrated clock generation and clock recovery

Manufacturer

Vitesse Semiconductor Corp.

Datasheet

1.VSC8114QB.pdf (24 pages)

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VSC8114

G52185-0, Rev 4.0

11/1/99

Data Sheet

Features

General Description

Unit (PLL) for high speed clock generation as well as a Clock and data Recovery Unit (CRU) with 8-bit serial-

to-parallel and parallel-to-serial data conversion. The PLL clock is used for serialization in the transmit direc-

tion (Mux). The recovered clock is used for deserialization in the receive direction (Demux). The demultiplexer

contains SONET/SDH frame detection and recovery. In addition, the device provides both facility and equip-

ment loopback modes and a loop time mode. The part is packaged in a 100PQFP with an integrated heat

spreader for optimum thermal performance and reduced cost. The VSC8114 provides an integrated solution for

ATM physical layers and SONET/SDH systems applications.

Functional Description

networks and the lower speed User Network Interface devices such as the PM5355 S/UNI-622. The VSC8114

converts 8 bit parallel data at 77.76Mb/s to a serial bit stream at 622.08Mb/s. The device also provides a Facility

Loopback function which loops the received high speed data and clock (optionally recovered on-chip) directly

to the high speed transmit outputs. A Clock Multiplier Unit (CMU) is integrated into the transmit circuit to gen-

erate the high speed clock for the serial output data stream from input reference frequencies of 19.44 or 77.76

MHz. The CMU can be bypassed with the received/recovered clock in loop timing mode, thus synchronizing

the entire part to a single clock. The block diagram on page 2 shows the major functional blocks associated with

the VSC8114.

allel output at 77.76MHz. A Clock Recovery Unit (CRU) is integrated into the receive circuit to recover the high

speed clock from the received serial data stream. The receive section provides an Equipment Loopback function

which will loop the low speed transmit data and clock back through the receive section to the 8 bit parallel out-

puts. The VSC8114 also provides the option of selecting between either its internal CRU’s clock and data sig-

nals, or optics containing a CRU clock and data signals. The receive section also contains a SONET/SDH frame

The VSC8114 is an ATM/SONET/SDH compatible transceiver integrating an on-chip Clock Multiplication

The VSC8114 is designed to provide a SONET/SDH compliant interface between the high speed optical

The receive section provides the serial-to-parallel conversion, converting 622Mb/s bit stream to an 8 bit par-

• Operates at STS-12/STM-4 (622.08Mb/s)

• Compatible with Industry ATM UNI Devices

• On Chip Clock Generation of the 622.08MHz

• On Chip Clock Recovery of the 622.08MHz

• 8-Bit Parallel TTL Interface with Parity Error

• SONET/SDH Frame Recovery

Data Rate

High Speed Clock (Mux)

High Speed Clock (Demux)

Detection and Generation

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

VITESSE SEMICONDUCTOR CORPORATION

SEMICONDUCTOR CORPORATION

with Integrated Clock Generation and Clock Recovery

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

• Loss of Signal (LOS) Input & LOS Detection

• +3.3V/5V Programmable PECL Serial Interface

• Provides Equipment, Facilities and Split Loop-

• Provide PECL Reference Clock Inputs

• Meets Bellcore, ITU and ANSI Specifications

• Low Power - 0.9Watts Typical

• 100 PQFP Package

back Modes as well as Loop Timing Mode

for Jitter Performance

Page 1

Related parts for VSC8114QB

VSC8114QB Summary of contents

Page 1

Data Sheet VSC8114 Features • Operates at STS-12/STM-4 (622.08Mb/s) Data Rate • Compatible with Industry ATM UNI Devices • On Chip Clock Generation of the 622.08MHz High Speed Clock (Mux) • On Chip Clock Recovery of the 622.08MHz High Speed ...

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery detector circuit which is used to provide frame pluses during the A1, A2 boundary in the serial to parallel con- verter. This only occurs when OOF is high. ...

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Data Sheet VSC8114 sion of the input reference clock. External control input REFSEL selects the multiply ratio of the CMU (see table 11). A divide-by-8 version of the CMU clock (TXLSCKOUT) should be used to synchronize the transmit interface of ...

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery PECL input LOSPECL to force the part into a Loss of Signal state. Most optics have a PECL output usually called “SD” or “FLAG” indicating the presence or ...

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Data Sheet VSC8114 Equipment Loopback The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the paral- lel to ...

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Loop Timing LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU is bypassed by using the receive clock (RXCLKIN), and ...

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Data Sheet VSC8114 Table 1: Recommended External Capacitor Values Reference Frequency Divide Ratio [MHz] 19.44 32 77.76 8 Clock Recovery The fully monolithic Clock Recovery Unit (CRU) consists of a Phase Detector, a Frequency Detector, a Loop Filter and a ...

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery J ( ITTER P P Bellcore Requirement 150 15 1.5 0.15 Data Latency The VSC8114 contains several operating modes, each of which exercise different logic paths ...

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Data Sheet VSC8114 AC Timing Characteristics Figure 8: Receive High Speed Data Input Timing Diagram RXCLKIN+ RXCLKIN- RXDATAIN+ RXDATAIN- Table 3: Receive High Speed Data Input Timing Table Parameter T Receive clock period RXCLK T Serial data setup time with ...

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Figure 10: Transmit High Speed Data Timing Diagram TXDATAOUT+ TXDATAOUT- Table 5: Transmit High Speed Data Timing Table Parameter T Transmit data width TXDAT TXLSCKOUT TXLSCKIN TXIN [7:0] ...

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Data Sheet VSC8114 AC Characteristics Table 7: PECL and TTL Outputs Parameter Description T TTL Output Rise Time R,TTL T TTL Output Fall Time F,TTL T PECL Output Rise Time R,PECL T PECL Output Fall Time F,PECL DC Characteristics Table ...

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Parameter Description Input LOW voltage V IL (TTL) Input HIGH current I IH (TTL) Input LOW current I IL (TTL) Power Dissipation Table 9: Power Supply Currents Parameter ...

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Data Sheet VSC8114 Clock Recovery Unit Table 10: Reference Frequency for the CRU CRUREFSEL 1 0 Clock Multiplier Unit Table 11: Reference Frequency Selection and Output Frequency Control REFSEL 1 0 Table 12: Clock Multiplier Unit Performance Name RCd Reference ...

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Package Pin Description Table 13: Pin Definitions Signal Pin FACLOOP 1 VDD 2 CRUEQLP 3 RESET 4 LOOPTIM0 5 N/C 6 REFSEL 7 N/C 8 VDDP 9 TXDATAOUT+ ...

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Data Sheet VSC8114 Signal Pin N/C 32 RXOUTP 33 VSS 34 RXOUT0 35 RXOUT1 36 VSS 37 RXOUT2 38 RXOUT3 39 VSS 40 RXOUT4 41 RXOUT5 42 VSS 43 RXOUT6 44 RXOUT7 45 VSS 46 RXLSCKOUT VDD ...

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Signal Pin CP2 66 VDDA 67 VDDA 68 VDDA 69 VSSA 70 VSSA 71 VSS 72 N N/C VSS 75 VDD 76 N/C 77 N/C 78 ...

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Data Sheet VSC8114 Package Information PIN 100 PIN 1 EXPOSED HEATSINK (NOTE 2) 9.0 X 9.0 (N0TE 2) PIN NOTES: (1) Drawings not to scale. (2) Two styles of exposed heat spreaders may be used; square or ...

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery The VSC8114 is manufactured in a 100PQFP package which is supplied by two different vendors. The crit- ical dimensions in the drawing represent the superset of dimensions for ...

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... VSC8114QB1 622Mb/s Mux/Dmux with CMU and CRU in 100 Pin PQFP Extended Temperature ambient (equivalent ambient to 115 C case) VSC8114QB2 622Mb/s Mux/Dmux with CMU and CRU in 100 Pin PQFP Industrial Temperature, -40 C ambient case Notice This document contains preliminary information about a new product in the preproduction phase of devel- opment ...

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Application Notes Interconnecting the Byte Clocks (TXLSCKOUT and TXLSCKIN) The byte clock (TXLSCKOUT and TXLSCKIN) on the VSC8114 has been brought off-chip to allow as much flexibility in ...

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Data Sheet VSC8114 Important note: The 11 ns max Tpd on the PM5355 assumes a 50pf load @ 60ps/pf, therefore the max delay is due to loading. The VSC8114 input (TXLSCKIN) plus package is about 6pf. Assuming ...

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Layout of the High Speed Signals The routing of the High Speed signals should be done using good high speed design practices. This would include using controlled impedance ...

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Data Sheet VSC8114 V +3 Current INPUT R R GND REFCLK and TTL Inputs G52185-0, Rev 4.0 11/1/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with ...

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ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Page 24 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8114 G52185-0, Rev 4.0 11/1/99 ...

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