AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 37
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AT32UC3A1256AU
Manufacturer Part Number
AT32UC3A1256AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A1256AU
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
69
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
32058KS–AVR32–01/12
10.11.8
10.11.9
10.11.10 Pulse Width Modulation Controller
Serial Synchronous Controller
Timer Counter
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RS485 with driver control signal
ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
IrDA modulation and demodulation
Test Modes
SPI Mode
Supports Connection of Two Peripheral DMA Controller Channels (PDC)
Provides serial synchronous communication links used in audio and telecom applications (with
CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)
Contains an independent receiver and transmitter and a common clock divider
Offers a configurable frame sync and data length
Receiver and transmitter can be programmed to start automatically or on detection of different
event on the frame sync signal
Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
Three 16-bit Timer Counter Channels
Wide range of functions including:
Each channel is user-configurable and contains:
Two global registers that act on all three TC Channels
7 channels, one 20-bit counter per channel
Common clock generator, providing Thirteen Different Clocks
Independent channel programming
– Optional Manchester Encoding
– NACK handling, error counter with repetition and iteration limit
– Communication at up to 115.2 Kbps
– Remote Loopback, Local Loopback, Automatic Echo
– Master or Slave
– Serial Clock Programmable Phase and Polarity
– SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency PBA/4
– Offers Buffer Transfer without Processor Intervention
– Frequency Measurement
– Event Counting
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
– A Modulo n counter providing eleven clocks
– Two independent Linear Dividers working on modulo n counter outputs
– Independent Enable Disable Commands
– Independent Clock
– Independent Period and Duty Cycle, with Double Bufferization
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
AT32UC3A
37