AT32UC3A1256AU Atmel Corporation, AT32UC3A1256AU Datasheet - Page 55

• Manufacturer Part Number: AT32UC3A1256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058KS–AVR32–01/12
Table 12-28. SDRAM Clock Signal.
Symbol
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
11
12
13
14
15
16
17
18
19
20
23
24
25
26
Parameter
Address Change before SDCK Rising Edge
Address Change after SDCK Rising Edge
Bank Change before SDCK Rising Edge
Bank Change after SDCK Rising Edge
CAS Low before SDCK Rising Edge
CAS High after SDCK Rising Edge
DQM Change before SDCK Rising Edge
DQM Change after SDCK Rising Edge
D0-D15 in Setup before SDCK Rising Edge
D0-D15 in Hold after SDCK Rising Edge
SDWE Low before SDCK Rising Edge
SDWE High after SDCK Rising Edge
D0-D15 Out Valid before SDCK Rising Edge
D0-D15 Out Valid after SDCK Rising Edge
AT32UC3A
Min
6.2
2.2
6.3
2.4
7.4
1.9
6.4
2.2
7.6
1.8
7.1
1.5
9
0
Units
ns
55