AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 87

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9. OCD system
9.1
9.1.1
9.1.2
9.1.2.1
32002F–03/2010
Overview
Features
OCD controller overview
Host, debugger, and emulator
The AVR32 CPU is targeted at a wide range of 32-bit applications. The CPU can be delivered in
very different implementations in various ASIC’s, ASSP’s, and standard parts to satisfy require-
ments for low-cost as well as high-speed markets. According to the cost sensitivity and
complexity of these applications, a similar span in debug complexity must be expected. While
some users expect very simple debug features, or none at all, others will demand full-speed
trace and RTOS debug support. This also applies to the debug tools: While the simplest devel-
opment takes place on simulators and development boards, most will require basic on-chip
debug emulators, and a few will require complex emulators with full-speed trace.
To match these criteria, the AVR32 OCD system is designed in accordance with the Nexus 2.0
standard (IEEE-ISTO 5001™-2003), which is a highly flexible and powerful open on-chip debug
standard for 32-bit microcontrollers.
The OCD system interfaces provides the external debugger with access to the on-chip debug
logic through the JTAG port and the Auxiliary (AUX) port, as shown in Figure 9-1. The operation
is described briefly below and in more detail in separate chapters.
At the host side, the user debugs his software using a source level debugger, which can read his
compiled and linked object code. The source level debugger accesses features in the emulator
and OCD system through an API (defined by the vendor or based on the Nexus recommenda-
tions), which constitutes the abstract interface between the source level debugger and the
emulator. The API translates high-level functions, such as setting breakpoints or reading mem-
ory areas, to sets of low level commands understood by the OCD controller. Certain operations
• Nexus compliant debug solution
• OCD supports any CPU speed
• Execute debug specific CPU instructions (debug code) from program memory monitor or
• Debug code can read and write all registers and data memory
• Debug code can communicate with debugger through the debug port
• Debug mode can be entered by external command, breakpoint instruction, or hardware
• Six program counter hardware breakpoints are supported
• Two data breakpoints are supported
• Breakpoints can be configured as watchpoints (flagged to the external debugger)
• Hardware breakpoints can be combined to give break on ranges
• Real-time program counter branch tracing
• Real-time data trace
• Real-time process trace
• Nexus Class 2+
external debugger
breakpoints
AVR32
87