AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 99

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.2.12
32002F–03/2010
OCD Interrupts
rently executing mode, only PID and DCCPU can be written. Illegal access to the registers will
be ignored with no error reporting.
Table 9-3.
To support custom debug protocols running in software the OCD system support giving inter-
rupts to the CPU when DCEMU is written or when DCCPU is read. A software protocol handler
can then be triggered by these interrupts instead of having to poll DCSR to see if the data in
DCCPU or DCEMU has been read or written.
To enable these interrupts the user must do the following:
Register
Development Control (DC)
Watchpoint Trigger (WT)
Data Trace Control (DTC)
Data Trace Start Address (DTSA) Channel 1 to
2
Data Trace End Address (DTEA) Channel 1 to
2
PC Breakpoint/Watchpoint Control (BWC)
Data Breakpoint/Watchpoint Control (BWC)
PC Breakpoint/Watchpoint Address (BWA)
Data Breakpoint/Watchpoint Address (BWA)
Breakpoint/Watchpoint Data (BWD)
Ownership Trace Process ID (PID)
Debug Instruction Register
Debug Program Counter
Debug Communication CPU (DCCPU)
Debug Communication Emulator (DCEMU)
• Program the interrupt controller with the correct priority and handler address for the interrupt.
• Enable the interrupts from the OCD by setting the corresponding bits in DCCR
OCD Register access
Can be written by JTAG
while CPU is running?
Yes
Yes
Can be written to disable /
enable trace channels.
Can only be written while
trace channel is disabled
Can only be written while
trace channel is disabled
Can be written to disable /
enable watchpoints /
breakpoints.
Can be written to disable /
enable watchpoints /
breakpoints.
Can only be written while
breakpoint / watchpoint is
disabled
Can only be written while
breakpoint / watchpoint is
disabled
Can only be written while
breakpoint / watchpoint is
disabled
Yes
No
No
Yes
Yes
Can be written by
CPU in Monitor
Mode?
Yes
Yes
Yes
Yes
Yes
Yes, if SR:DM is set.
Yes, if SR:DM is set.
Yes, if SR:DM is set
or breakpoint
disabled.
Yes, if SR:DM is set
or breakpoint
disabled.
Yes, if SR:DM is set
or breakpoint
disabled.
No
No
Yes
Yes
Yes
AVR32
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