AT32UC3A4256 Atmel Corporation, AT32UC3A4256 Datasheet - Page 341
AT32UC3A4256
Manufacturer Part Number
AT32UC3A4256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Quantity
Price
Part Number:
AT32UC3A4256S-C1UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
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Manufacturer:
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Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 341 of 1012
- Download datasheet (16Mb)
32072G–11/2011
The transfer is similar to that shown in
The DMA Transfer flow is shown in
Figure 19-15. Multi-block Transfer with Source Address Auto-reloaded and Contiguous Desti-
7. The DMA transfer proceeds as follows:
Complete or Transfer Complete interrupts, or poll for the Channel Enable (ChEn-
Reg.CH_EN) bit until it is cleared by hardware, to detect when the transfer is complete.
If the DMACA is not in Row 1, the next step is performed.
a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is un-
b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is
masked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the
block complete interrupt when the block transfer has completed. It then stalls until
the block complete interrupt is cleared by software. If the next block is to be the last
block in the DMA transfer, then the block complete ISR (interrupt service routine)
should clear the source reload bit, CFGx.RELOAD_SR. This puts the DMACA into
Row1 as shown in
the DMA transfer then the source reload bit should remain enabled to keep the
DMACA in Row3 as shown in
masked (MaskBlock[x] = 1’b0, where x is the channel number) then hardware does
not stall until it detects a write to the block complete interrupt clear register but
starts the next block transfer immediately. In this case software must clear the
source reload bit, CFGx.RELOAD_SR, to put the device into ROW 1 of
on page 326
Address of
Source Layer
nation Address
SAR
before the last block of the DMA transfer has completed.
Source Blocks
Table 19-1 on page
Figure 19-16 on page
Figure 19-15 on page
Table 19-1 on page
326. If the next block is not the last block in
Block2
Block0
Block1
Destination Blocks
342.
326.
341.
DAR(2)
DAR(0)
DAR(1)
Destination Layer
Address of
Table 19-1
341
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