AT32UC3A4256 Atmel Corporation, AT32UC3A4256 Datasheet - Page 450
AT32UC3A4256
Manufacturer Part Number
AT32UC3A4256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A4256S-C1UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3A4256S-U
Manufacturer:
ST
Quantity:
79
Part Number:
AT32UC3A4256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 450 of 1012
- Download datasheet (16Mb)
32072G–11/2011
The TWI transfers require the receiver to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the mas-
ter to pull it down in order to generate the acknowledge. The slave polls the data line during this
clock pulse and sets the NAK bit in SR if the master does not acknowledge the data byte. A NAK
means that the master does not wish to receive additional data bytes. As with the other status
bits, an interrupt can be generated if enabled in the Interrupt Enable Register (IER).
SR.TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.
The end of the complete transfer is marked by the SR.TCOMP bit changing from zero to one.
See
Figure 22-7. Slave Transmitter with One Data Byte
4. NBYTES is updated. If CR.CUP is one, NBYTES is incremented, otherwise NBYTES is
5. After each data byte has been transmitted, the master transmits an ACK (Acknowl-
6. If STOP is received, SR.TCOMP and SR.STO will be set.
7. If REPEATED START is received, SR.REP will be set.
Figure 22-7
decremented.
edge) or NAK (Not Acknowledge) bit. If a NAK bit is received by the TWIS, the SR.NAK
bit is set. Note that this is done two CLK_TWIS cycles after TWCK has been sampled
by the TWIS to be HIGH (see
ished, and the TWIS will wait for a STOP or REPEATED START. If an ACK bit is
received, the SR.NAK bit remains LOW. The ACK indicates that more data should be
transmitted, jump to step 2. At the end of the ACK/NAK clock cycle, the Byte Transfer
Finished (SR.BTF) bit is set. Note that this is done two CLK_TWIS cycles after TWCK
has been sampled by the TWIS to be LOW (see
event that SR.NAK bit is set, it must not be cleared before the SR.BTF bit is set to
ensure correct TWIS behavior.
TCOMP
TXRDY
TWD
Write THR (DATA)
and
NBYTES set to 1
S
Figure
DADR
22-8.
Figure
R
22-9). The NAK indicates that the transfer is fin-
A
DATA
Figure
22-9). Also note that in the
N
STOP sent by master
P
450
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