AT32UC3A4256 Atmel Corporation, AT32UC3A4256 Datasheet - Page 850

• Manufacturer Part Number: AT32UC3A4256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4256

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.7.12
Name:
Access Type:
Offset:
Reset Value:
• ACKRCVE: Boot Operation Acknowledge Error
• ACKRCV: Boot Operation Acknowledge Received
• UNRE: Underrun Error
• OVRE: Overrun Error
• XFRDONE: Transfer Done
• FIFOEMPTY: FIFO empty
• DMADONE: DMA Transfer done
• BLKOVRE: DMA Block Overrun Error
32072G–11/2011
TXBUFE
CSTOE
ENDTX
UNRE
31
23
15
7
This bit is set when a corrupted Boot Acknowlegde signal has been received.
This bit is cleared by reading the SR register.
This bit is set when a Boot acknowledge signal has been received.
This bit is cleared by reading the SR register.
This bit is set when at least one eight-bit data has been sent without valid information (not written).
This bit is cleared when sending a new data transfer command if the Flow Error bit reset control mode in Configuration Register
(CFG.FERRCTRL) is zero or when reading the SR register if CFG.FERRCTRL is one.
This bit is set when at least one 8-bit received data has been lost (not read).
This bit is cleared when sending a new data transfer command if CFG.FERRCTRL is zero, or when reading the SR register if
CFG.FERRCTRL is one.
This bit is set when the CR register is ready to operate and the data bus is in the idle state.
This bit is cleared when a transfer is in progress.
This bit is set when the FIFO is empty.
This bit is cleared when the FIFO contains at least one byte.
This bit is set when the DMA buffer transfer is completed.
This bit is cleared when reading the SR register.
This bit is set when a new block of data is received and the DMA controller has not started to move the current pending block.
This bit is cleared when reading the SR register.
Status Register
RXBUFF
ENDRX
OVRE
DTOE
30
22
14
6
SR
Read-only
0x040
0x0C000025
ACKRCVE
NOTBUSY
DCRCE
CSRCV
29
21
13
5
SDIOWAIT
ACKRCV
RTOE
DTIP
28
20
12
4
XFRDONE
RENDE
BLKE
27
19
11
3
-
FIFOEMPTY
RCRCE
TXRDY
26
18
10
2
-
DMADONE
SDIOIRQB
RXRDY
RDIRE
25
17
9
1
SDIOIRQA
BLKOVRE
CMDRDY
RINDE
24
16
8
0
850