AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 1064
AT32UC3C164C
Manufacturer Part Number
AT32UC3C164C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C164C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C164C-AUR
Manufacturer:
ATMEL
Quantity:
1 240
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34.7.7
Name:
Access Type:
Offset:
Reset Value:
• CLKEN: QDEC Counter Clock Status
• CNTDIR: Counter Direction
• TRIGGER: Trigger Event Occurrence
• QDERR: Illegal Quadrature Signals Transition
• OVR: Overrun Capture
• DIRINV: Count Direction Inversion
• IDXERR: Index Error
• RCRO: Revolution Counter Roll Over
• PCRO: Position Counter Roll Over
32117C–AVR-08/11
OVR
31
23
15
-
-
-
7
This bit is cleared when the QDEC and CLK_QDEC_INT has been disabled
This bit is set when the QDEC and CLK_QDEC_INT has been enabled
This bit is cleared when the counter counts up
This bit is set when the counter counts down
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when the trigger event has occurred
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when an illegal transition of quadrature signals has occurred
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when the overrun capture event has occurred
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when the count direction has changed
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when an index error has occurred
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when the revolution counter has rolled over
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when the position counter has rolled over
Status Register
DIRINV
30
22
14
SR
Read-only
0x1C
0x00000000
–
-
-
6
IDXERR
29
21
13
-
-
–
5
RCRO
28
20
12
-
-
–
4
PCRO
27
19
11
-
-
–
3
CAP
26
18
10
-
-
–
2
TRIGGER
CLKEN
CMP
25
17
–
9
1
AT32UC3C
CNTDIR
QDERR
QEPI
24
16
–
8
0
1064
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