AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 1212
AT32UC3C164C
Manufacturer Part Number
AT32UC3C164C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C164C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C164C-AUR
Manufacturer:
ATMEL
Quantity:
1 240
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39.5
Table 39-7.
39.5.1
32117C–AVR-08/11
Instruction
OPCODE
Others
0x0C
0x0F
0x1C
0x1F
0x01
0x02
0x03
0x04
0x06
0x10
0x11
0x12
0x13
0x14
0x15
0x17
JTAG Instruction Summary
Security Restrictions
JTAG Instruction Summary
SAMPLE_PRELOAD
EXTEST
CLAMP
AVR_RESET
CHIP_ERASE
NEXUS_ACCESS
MEMORY_WORD_ACCESS
MEMORY_SERVICE
MEMORY_SIZED_ACCESS
SYNC
HALT
N/A
Instruction
IDCODE
INTEST
MEMORY_BLOCK_ACCESS
CANCEL_ACCESS
BYPASS
The implemented JTAG instructions in the 32-bit AVR are shown in the table below.
When the security fuse in the Flash is programmed, the following JTAG instructions are
restricted:
For description of what memory locations remain accessible, please refer to the SAB address
map.
Full access to these instructions is re-enabled when the security fuse is erased by the
CHIP_ERASE JTAG instruction.
• Perform a CHIP_ERASE to clear the security bit. NOTE : This will erase all the contents of the
• NEXUS_ACCESS
• MEMORY_WORD_ACCESS
• MEMORY_BLOCK_ACCESS
• MEMORY_SIZED_ACCESS
non-volatile memory.
Description
Select the 32-bit Device Identification register as data register.
Take a snapshot of external pin values without affecting system operation.
Select boundary-scan chain as data register for testing circuitry external to
the device.
Select boundary-scan chain for internal testing of the device.
Bypass device through Bypass register, while driving outputs from boundary-
scan register.
Apply or remove a static reset to the device
Erase the device
Select the SAB Address and Data registers as data register for the TAP. The
registers are accessed in Nexus mode.
Select the SAB Address and Data registers as data register for the TAP.
Select the SAB Data register as data register for the TAP. The address is
auto-incremented.
Cancel an ongoing Nexus or Memory access.
Select the SAB Address and Data registers as data register for the TAP. The
registers are accessed in Memory Service mode.
Select the SAB Address and Data registers as data register for the TAP.
Synchronization counter
Halt the CPU for safe programming.
Bypass this device through the bypass register.
Acts as BYPASS
AT32UC3C
1212
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