AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 1153
AT32UC3C164C
Manufacturer Part Number
AT32UC3C164C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C164C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C164C-AUR
Manufacturer:
ATMEL
Quantity:
1 240
- AT32UC3A0128 PDF datasheet
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37.6.3
37.6.4
32117C–AVR-08/11
Interrupts
Peripheral Events
In an ideal DAC, gain is 1 and offset 0.
An interrupt request will be generated if the corresponding bit in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable
Register (IDR). The interrupt request remains active until the corresponding bit in SR is cleared
by writing a one to the corresponding bit in the Status Clear Register (SCR).
After processing a channel input data, if the data input buffer is empty, the DACIFB signals a
data empty interrupt to the interrupt controller.
An underrun interrupt will be generated if two consecutive trigger events are issued without any
new channel data being fed to the DACIFB in the meantime.
An overrun interrupt will be generated if an additional channel data is sent to the DACIFB while
the input buffer is already full.
Channel conversions can be triggered by an independent event source. A simple arbiter priori-
tizes trigger event requests if the two channels are activated at the same time.
Trigger events for both channels are taken either from the PEVC input or from the DACIFB inter-
nal trigger timers. These two timers are set up separately and both use PrescalerClock as their
reference clock (see the TRA and TRB registers).
V
DACxX
= gain x (DATA
CHx
/ 0xFFF) + offset
AT32UC3C
1153
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