AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 704
AT32UC3C164C
Manufacturer Part Number
AT32UC3C164C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C164C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C164C-AUR
Manufacturer:
ATMEL
Quantity:
1 240
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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- Download datasheet (20Mb)
Figure 27-7. Master Write with Multiple Data Bytes
27.8.4
32117C–AVR-08/11
SR.IDLE
TXRDY
TWD
Master Receiver Mode
NBYTES set to n
S
Write THR
(DATAn)
DADR
does not acknowledge the data byte. As with the other status bits, an interrupt can be generated
if enabled in the Interrupt Enable Register (IER).
TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.
The end of a command is marked by writing a one to the SR.CCOMP bit. See
Figure
Figure 27-6. Master Write with One Data Byte
A START condition is transmitted and master receiver mode is initiated when the bus is free and
CMDR has been written with START=1 and READ=1. START and SADR+R will then be trans-
mitted. During the address acknowledge clock pulse (9th pulse), the master releases the data
line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The master
polls the data line during this clock pulse and writes a one to the Address Not Acknowledged bit
(ANAK) in the Status Register if no slave acknowledges the address.
After the address phase, the following is repeated:
while (NBYTES>0)
SR.IDLE
1. Wait until RHR is empty, stretching low period of TWCK. SR.RXRDY indicates the state
2. Release TWCK generating a clock that the slave uses to transmit a data byte.
3. Place the received data byte in RHR, write a one to RXRDY.
4. If NBYTES=0, generate a NAK after the data byte, otherwise generate an ACK.
TXRDY
W
of RHR. Software or the Peripheral DMA Controller must read any data byte present in
RHR.
TWD
27-7.
A
Write THR (DATA)
NBYTES set to 1
S
(DATAn+1)
Write THR
DATAn
DADR
A
W
A
DATAn+5
Last data sent
(DATAn+m)
Write THR
DATA
(ACK received and NBYTES=0)
A
STOP sent automatically
A
DATAn+m
P
(ACK received and NBYTES=0)
STOP sent automatically
A
AT32UC3C
P
Figure 27-6
and
704
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