AT89C51AC3 Atmel Corporation, AT89C51AC3 Datasheet - Page 107

• Manufacturer Part Number: AT89C51AC3
• Manufacturer: Atmel Corporation

Specifications of AT89C51AC3

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 32
• Spi: 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 2.25
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

ADC Converter
Operation
Voltage Conversion
Clock Selection
4383D–8051–02/08
A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).
After completion of the A/D conversion, the ADSST bit is cleared by hardware.
The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is
available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is
set, an interrupt occur when flag ADEOC is set (see Figure 62). Clear this flag for re-
arming the interrupt.
The bits SCH0 to SCH2 in ADCON register are used for the analog input channel
selection.
Table 57. Selected Analog input
When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If
the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between
VAREF and VAGND are a straight-line linear conversion. All other voltages will result in
3FFh if greater than VAREF and 000h if less than VAGND.
Note that ADCIN should not exceed VAREF absolute maximum range! (See section
“AC-DC”)
The ADC clock is the same as CPU.
The maximum clock frequency is defined in the DC parmeters for A/D converter. A pres-
caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency.
f
if PRS > 0 then f
if PRS = 0 then f
ADC
= fcpu clock/ (4 (or 2 in X2 mode)* PRS )
SCH2
0
0
0
0
1
1
1
1
ADC
ADC
= F
= F
periph
periph
/ 2 x PRS
/ 64
SCH1
0
0
1
1
0
0
1
1
SCH0
0
1
0
1
0
1
0
1
Selected Analog input
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
107