AT89C51AC3 Atmel Corporation, AT89C51AC3 Datasheet - Page 50

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AT89C51AC3

Manufacturer Part Number
AT89C51AC3
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT89C51AC3

Flash (kbytes)
64 Kbytes
Max. Operating Frequency
60 MHz
Cpu
8051-12C
Max I/o Pins
32
Spi
1
Uart
1
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
62.5
Sram (kbytes)
2.25
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
3.0 to 5.5
Timers
4
Isp
UART
Watchdog
Yes

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Reset the Column Latches
Error Reports
Flash Programming Sequence
Errors
50
AT89C51AC3
Figure 27. Hardware Programming Procedure
An automatic reset of the column latches is performed after a successful Flash
write sequence. User can also reset the column latches manually, for instance
to reload the column latches before writing the Flash. The following procedure is
summarized below.
When a wrong sequence is detected, the SEQERR bit in FSTA register is set. Possible
wrong sequence are :
The SEQERR bit can be cleared
When multiple pages are written into the Flash, the user should check FSTA for errors
after each write page sequences, not only at the end of the multiple write pages.
Save and disable the interrupts.
Launch the reset by writing the data sequence 56h followed by A6h in FCON
register (only from FM1).
Restore the interrupts.
MOV FCON, 5xh instruction not immediately followed by a MOV FCON, Ax
instruction.
A write Flash sequence is launched while no data were loaded in the column latches
By software
By hardware when a correct programming sequence is completed
Exec: MOVX @DPTR, A
Save and Disable IT
Programming
Flash Spaces
End Loading
FCON = 0Ch
DPTR = 00h
ACC = Data
Data Load
Restore IT
EA = 0
Launch Programming
Save and Disable IT
End Programming
FCON = A4h
FCON = 54h
FCON = 00h
Clear Mode
4383D–8051–02/08
Cleared?
RestoreIT
FBusy
EA = 0

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