AT90CAN32 Atmel Corporation, AT90CAN32 Datasheet - Page 30

• Manufacturer Part Number: AT90CAN32
• Manufacturer: Atmel Corporation

Specifications of AT90CAN32

• Flash (kbytes): 32 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

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AT90CAN32/64/128
address actually is driven on the bus. The access time cannot exceed the time from the ALE
pulse must be asserted low until data is stable during a read sequence (see t
in
tional feature, it is possible to divide the external memory space in two sectors with individual
wait-state settings. This makes it possible to connect two different memory devices with different
timing requirements to the same XMEM interface. For XMEM interface timing details, please
refer to
Memory Characteristics” on page
Note that the XMEM interface is asynchronous and that the waveforms in the following figures
are related to the internal system clock. The skew between the internal and external clock
(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-
quently, the XMEM interface is not suited for synchronous operation.
Figure 4-6.
Note:
Figure 4-7.
Table 26-7
Table 26-7
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
System Clock (CLK
SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction
accesses the RAM (internal or external).
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
through
External Data Memory Cycles no Wait-state (SRWn1=0 and SRWn0=0)
External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1
System Clock (CLK
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
through
DA7:0
A15:8
CPU
ALE
WR
Table
RD
)
Prev. addr.
Prev. data
Prev. data
Prev. data
DA7:0
A15:8
CPU
ALE
WR
RD
26-14). The different wait-states are set up in software. As an addi-
Table 26-14
)
Prev. addr.
Prev. data
Prev. data
Prev. data
T1
375.
T1
and
Address
Address
Address
T2
Figure 26-6
Address
Address
Address
XX
T2
XX
XXXXX
Address
T3
Data
Data
Data
to
Figure 26-9
Address
T3
Data
Data
Data
T4
XXXXXXXX
in the
T4
LLRL
(1)
“External Data
+ t
T5
7679H–CAN–08/08
RLRH
(1)
- t
DVRH