AT90CAN32 Atmel Corporation, AT90CAN32 Datasheet - Page 37

• Manufacturer Part Number: AT90CAN32
• Manufacturer: Atmel Corporation

Specifications of AT90CAN32

• Flash (kbytes): 32 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5. System Clock
5.1
5.1.1
5.1.2
5.1.3
7679H–CAN–08/08
Clock Systems and their Distribution
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
I/O
Figure 5-1
need not be active at a given time. In order to reduce power consumption, the clocks to unused
modules can be halted by using different sleep modes, as described in
Sleep Modes” on page
Figure 5-1.
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, CAN,
USART. The I/O clock is also used by the External Interrupt module, but note that some external
interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the
I/O clock is halted. Also note that address recognition in the TWI module is carried out asynchro-
nously when clk
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
CPU
FLASH
CLKO
presents the principal clock systems in the AVR and their distribution. All of the clocks
Timer/Counter2
External Clock
Timer/Counter2
Asynchronous
Clock Distribution
I/O
CKOUT Fuse
is halted, enabling TWI address reception in all sleep modes.
Multiplexer
46. The clock systems are detailed below.
TOSC1
Timer/Counter2
Controller
Oscillator
CAN
TOSC2
General I/O
Modules
clk
External Clock
clk
ASY
I/O
Multiplexer
Prescaler
Control Unit
AVR Clock
Clock
ADC
clk
XTAL1
ADC
Oscillator
Crystal
AT90CAN32/64/128
Source clock
XTAL2
CPU Core
clk
clk
Reset Logic
CPU
FLASH
Watchdog clock
“Power Management and
Crystal Oscillator
Low-frequency
Watchdog Timer
RAM
Watchdog
Oscillator
Calibrated RC
Flash and
EEPROM
Oscillator
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