AT90CAN32 Atmel Corporation, AT90CAN32 Datasheet - Page 418

• Manufacturer Part Number: AT90CAN32
• Manufacturer: Atmel Corporation

Specifications of AT90CAN32

• Flash (kbytes): 32 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

418
AT90CAN32/64/128
CAN 2.0B
CAN 2.0A
15-bit CRC
15-bit CRC
5. Asynchronous Timer-2 wakes up without interrupt
CRC
Field
CRC
Field
minimum delay will be 39-bit time in CAN2.0B. See CAN2.0A CAN2.0B frame timings
below.
Workaround implementation
The workaround is to have the last MOb (MOb14) as "spy" enabled all the time; it is the MOb
of lowest priority. If a MOb other than MOb14 is programmed in receive mode and its accep-
tance filter matches with the incoming message ID, this MOb will take the message. MOb14
will only take messages than no other MObs will have accepted. MOb14 will need to be re-
enabled fast enough to manage back to back frames. The deadline to do this is the begin-
ning of DLC slot of incoming frames as explained above.
Minimum code to insert in CAN interrupt routine:
__interrupt void can_int_handler(void)
The asynchronous timer can wake from sleep without giving interrupt. The error only occurs
if the interrupt flag(s) is cleared by software less than 4 cycles before going to sleep and this
clear is done exactly when it is supposed to be set (compare match or overflow). Only the
interrupts flags are affected by the clear, not the signal witch is used to wake up the part.
Problem fix / workaround
No known workaround, try to lock the code to avoid such a timing.
CRC
CRC
del.
del.
{
if ((CANSIT1 & 0x40) == 0x40 )
........
........
}
ACK
ACK
Field
ACK
Field
ACK
{
CANPAGE = (0x0E << 4);
CANSTMOB = 0x00;
CANCDMOB = 0x88;
}
ACK
ACK
del.
del.
End of Frame
End of Frame
7 bits
7 bits
(RXOK)
(RXOK)
T
T
1
1
mission
mission
3 bits
3 bits
Inter-
Inter-
SOF
SOF
SOF
SOF
19-bit time minimum
11-bit base identifier
11-bit identifier
/* select MOb14 */
/* reset MOb14 status */
/* reception enable */
IDT28..18
ID10..0
/* MOb14 interrupt (SIT14=1) */
Arbitration
Field
39-bit time minimum
RTR IDE
SRR IDE
Arbitration
Field
r0
Control
Field
T
18-bit identifier extension
2
4-bit DLC
DLC4..0
ID17..0
RTR
r1
r0
7679H–CAN–08/08
Control
Field
T
2
4-bit DLC
DLC4..0