AT90CAN32 Atmel Corporation, AT90CAN32 Datasheet - Page 77
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AT90CAN32
Manufacturer Part Number
AT90CAN32
Description
Manufacturer
Atmel Corporation
Specifications of AT90CAN32
Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Can
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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7679H–CAN–08/08
MOSI, SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a
slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is
enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB2 bit.
• SCK – Port B, Bit 1
SCK, Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a
slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is
enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB1 bit.
• SS – Port B, Bit 0
SS, Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.
Table 9-7
in
nal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
Table 9-7
in
Table 9-7.
Note:
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Figure 9-5 on page
Figure 9-5 on page
1. See
and
and
Table 9-8
Overriding Signals for Alternate Functions in PB7..PB4
Table 9-8
“Output Compare Modulator - OCM” on page 165
PB7/OC0A/OC1C
0
0
0
0
OC0A/OC1C
ENABLE
OC0A/OC1C
0
0
0
–
–
72.
72. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO sig-
relates the alternate functions of Port B to the overriding signals shown
relate the alternate functions of Port B to the overriding signals shown
(1)
(1)
PB6/OC1B
0
0
0
0
OC1B ENABLE
OC1B
0
0
0
–
–
AT90CAN32/64/128
PB5/OC1A
0
0
0
0
OC1A ENABLE
OC1A
0
0
0
–
–
for details.
PB4/OC2A
0
0
0
0
OC2A ENABLE
OC2A
0
0
0
–
–
77
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