ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 141

• Manufacturer Part Number: ATmega16HVB
• Manufacturer: Atmel Corporation

Specifications of ATmega16HVB

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 17
• Ext Interrupts: 15
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

24.7.6
24.7.7
8042D–AVR–10/11
BPSCD – Battery Protection Short-circuit Detection Level Register
BPDOCD – Battery Protection Discharge-Over-current Detection Level Register
Table 24-4.
Notes:
Note:
• Bits 7:0 – SCDL[7:0]: Short-circuit Detection Level
These bits sets the R
as defined in
Note:
• Bits 7:0 – DOCDL[7:0]: Discharge Over-current Detection Level
These bits sets the R
Table 24-5 on page
Note:
Bit
(0xF5)
Read/Write
Initial Value
Bit
(0xF6)
Read/Write
Initial Value
1. The actual value depends on the actual frequency of the
2. Initial value.
3. An additional delay T
Due to synchronization of parameters between clock domains, a guard time of three ULP oscilla-
tor cycles plus three CPU clock cycles is required between each time the BPHCTR register is
written. Any writing to the BPHCTR register during this period will be ignored.
Due to synchronization of parameters between clock domains, a guard time of three ULP oscilla-
tor cycles plus three CPU clock cycles is required between each time the BPSCD register is
written. Any writing to the BPSCD register during this period will be ignored.
Due to synchronization of parameters between clock domains, a guard time of three ULP oscilla-
tor cycles plus three CPU clock cycles is required between each time the BPDOCD register is
written. Any writing to the BPDOCD register during this period will be ignored.
page
the initialization of the protection circuitry. For the Discharge High-Current protection, this
applies when enabling the Discharge FET. For Charge High-Current protection, this applies
when enabling the Charge FET. With nominal ULP frequency this delay is maximum 0.2ms.
Table 24-5 on page
High-current protection reaction time. HCPT[5:0] with corresponding high-current
delay time. (Continued)
R/W
R/W
27. See
7
1
7
1
142.
SENSE
0x3E
0x3F
SENSE
...
”Electrical characteristics” on page
R/W
R/W
6
1
6
1
voltage level for detection of Short-circuit in the Discharge Direction,
voltage level for detection of Discharge Over-current, as defined in
High-current protection reaction time
d
can be expected after enabling the corresponding FET. This is related to
142.
R/W
R/W
5
1
5
1
R/W
R/W
4
1
4
1
DOCDL[7:0]
SCDL[7:0]
R/W
ATmega16HVB/32HVB
R/W
3
0
3
0
225.
(122ms - 124ms) + T
(124ms - 126ms) + T
R/W
R/W
2
0
”Ultra Low Power RC oscillator” on
2
0
(1)
R/W
R/W
...
1
1
1
1
R/W
R/W
d
d
0
1
0
1
(3)
(3)
BPDOCD
BPSCD
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