ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 179

• Manufacturer Part Number: ATmega16HVB
• Manufacturer: Atmel Corporation

Specifications of ATmega16HVB

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 17
• Ext Interrupts: 15
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

27.9
8042D–AVR–10/11
Bus connect/disconnect for two-wire serial interface
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
This is summarized in
Figure 27-21. Possible status codes caused by arbitration.
The Bus Connect/Disconnect module is an addition to the TWI Interface. Based on a configura-
tion bit, an interrupt can be generated either when the TWI bus is connected or disconnected.
Figure 27-22 on page 180
are the TWI data and clock lines, respectively.
When the TWI bus is connected, both the SDA and the SCL lines will become high simultane-
ously. If the TWBCIP bit is cleared, the interrupt will be executed if enabled. Once the bus is
connected, the TWBCIP bit should be set. This enables detection of when the bus is discon-
nected, and prevents repetitive interrupts every time both the SDA and SCL lines are high (for
example bus IDLE state).
When the TWI bus is disconnected, both the SDA and the SCL lines will become low simultane-
ously. If the TWBCIP bit is set, the interrupt will be executed if enabled and if both lines remain
low for a configurable time period. By adding this time constraint, unwanted interrupts caused by
both lines going low during normal bus communication is prevented. Once the bus is discon-
nected, the TWBCIP bit should be cleared. This enables detection of when the bus is connected,
and prevents repetitive interrupts if the SCL and SDA lines remain low.
to output a one on SDA while another master outputs a zero will lose the arbitration. Losing
masters will switch to not addressed Slave mode or wait until the bus is free and transmit a new
START condition, depending on application software action
SLA bits. Masters trying to output a one on SDA while another master outputs a zero will lose
the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are
being addressed by the winning master. If addressed, they will switch to SR or ST mode,
depending on the value of the READ/WRITE bit. If they are not being addressed, they will
switch to not addressed Slave mode or wait until the bus is free and transmit a new START
condition, depending on application software action
START
Address / General Call
Figure
Direction
received
Own
Yes
Arbitration lost in SLA
illustrates the Bus Connect/Disconnect logic, where SDA and SCL
SLA
27-21. Possible status values are given in circles.
Read
Write
No
68/78
38
B0
Arbitration lost in Data
ATmega16HVB/32HVB
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
Data
STOP
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