ATmega325P Atmel Corporation, ATmega325P Datasheet - Page 240

• Manufacturer Part Number: ATmega325P
• Manufacturer: Atmel Corporation

Specifications of ATmega325P

• Flash (kbytes): 32 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 17
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 23-5.
240
Step
1
2
3
4
5
6
7
8
9
10
11
ATmega325P/3250P
Actions
SAMPLE_PR
ELOAD
EXTEST
Verify the
COMP bit
scanned out to
be 0
Verify the
COMP bit
scanned out to
be 1
Algorithm for Using the ADC
• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low
As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
The recommended values from
rithm in
“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register
with the succeeding columns. The verification should be done on the data scanned out when
scanning in the data on the same row in the table.
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
ADCEN
(Sample mode).
1
1
1
1
1
1
1
1
1
1
1
Table
DAC
23-5. Only the DAC and port pin values of the Scan Chain are shown. The column
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
0x143
0x143
0x200
The lower limit is:
The upper limit is:
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
Table 23-4
1024 1,5V 0,95 5V
1024 1,5V 1,05 5V
HOLD
1
0
1
1
1
1
0
1
1
1
1
⋅
⋅
are used unless other values are given in the algo-
⋅
⋅
PRECH
⁄
1
1
1
1
0
1
1
1
1
0
1
⁄
=
=
291
323
PA3.
Data
CC
=
0
0
0
0
0
0
0
0
0
0
0
=
.
0x123
0x143
PA3.
Control
hold,max
0
0
0
0
0
0
0
0
0
0
0
8023F–AVR–07/09
PA3.
Pull-up_
Enable
0
0
0
0
0
0
0
0
0
0
0