ATmega325P Atmel Corporation, ATmega325P Datasheet - Page 51

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ATmega325P

Manufacturer Part Number
ATmega325P
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega325P

Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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10.5.2
8023F–AVR–07/09
WDTCR – Watchdog Timer Control Register
• Bits 7:5 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. This bit must also be set when
changing the prescaler bits. See
Watchdog Timer” on page
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit
has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm
described above.
• Bits 2:0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Time-out Periods
are shown in
Table 10-2.
Bit
(0x60)
Read/Write
Initial Value
WDP2
to WDE even though it is set to one before the disable operation starts.
0
0
0
0
1
1
1
1
WDP1
Table 10-2 on page
0
0
1
1
0
0
1
1
Watchdog Timer Prescale Select
R
7
0
See Section “10.4.1” on page 49.
WDP0
0
1
0
1
0
1
0
1
R
6
0
49.
Oscillator Cycles
Number of WDT
51.
1,024K cycles
2,048K cycles
128K cycles
256K cycles
512K cycles
R
”Timed Sequences for Changing the Configuration of the
16K cycles
32K cycles
64K cycles
5
0
WDCE
R/W
4
0
WDE
R/W
3
0
Typical Time-out at
ATmega325P/3250P
V
CC
17.1 ms
34.3 ms
68.5 ms
0.14 s
0.27 s
0.55 s
WDP2
1.1 s
2.2 s
R/W
= 3.0V
2
0
WDP1
R/W
1
0
Typical Time-out at
WDP0
R/W
V
0
0
CC
16.3 ms
32.5 ms
65 ms
0.13 s
0.26 s
0.52 s
1.0 s
2.1 s
= 5.0V
WDTCR
51

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