ATmega48 Atmel Corporation, ATmega48 Datasheet - Page 157

• Manufacturer Part Number: ATmega48
• Manufacturer: Atmel Corporation

Specifications of ATmega48

• Flash (kbytes): 4 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 24
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 256
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.11.3
18.11.4
2545T–AVR–05/11
TCNT2 – Timer/counter register
OCR2A – Output compare register A
A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2B as TOP.
The FOC2B bit is always read as zero.
• Bits 5:4 – Res: Reserved bits
These bits are reserved bits in the Atmel ATmega48/88/168 and will always read as zero.
• Bit 3 – WGM22: Waveform generation mode
See the description in the
• Bit 2:0 – CS22:0: Clock select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
18-9.
Table 18-9.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers.
Bit
(0xB2)
Read/write
Initial value
Bit
(0xB3)
Read/write
Initial value
CS22
0
0
0
0
1
1
1
1
Clock select bit description.
R/W
R/W
7
0
7
0
CS21
0
0
1
1
0
0
1
1
R/W
R/W
“TCCR2A – Timer/counter control register A” on page
6
0
6
0
CS20
R/W
R/W
0
1
0
1
0
1
0
1
5
0
5
0
R/W
R/W
Description
No clock source (timer/counter stopped)
clk
clk
clk
clk
clk
clk
clk
4
0
4
0
OCR2A[7:0]
TCNT2[7:0]
T2S
T2S
T2S
T2S
T2S
T
T
2
2
S
S
/256 (from prescaler)
/1024 (from prescaler)
/(no prescaling)
/8 (from prescaler)
/32 (from prescaler)
/64 (from prescaler)
/128 (from prescaler)
R/W
R/W
3
0
3
0
R/W
R/W
ATmega48/88/168
2
0
2
0
R/W
R/W
1
0
1
0
R/W
R/W
153.
0
0
0
0
OCR2A
TCNT2
Table
157