ATmega640 Atmel Corporation, ATmega640 Datasheet - Page 375
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ATmega640
Manufacturer Part Number
ATmega640
Description
Manufacturer
Atmel Corporation
Specifications of ATmega640
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
86
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
1
Uart
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
16
Input Capture Channels
4
Pwm Channels
15
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Quantity
Price
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31.7
2549N–AVR–05/11
5. This requirement applies to all ATmega640/1280/1281/2560/2561 2-wire Serial Interface operation. Other devices con-
6. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/f
7. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/f
SPI Timing Characteristics
nected to the 2-wire Serial Bus need only obey the general f
must be greater than 6MHz for the low time requirement to be strictly met at f
low time requirement will not be strictly met for f
devices connected to the bus may communicate at full speed (400kHz) with other ATmega640/1280/1281/2560/2561
devices, as well as any other device with a proper t
Figure 31-6. 2-wire Serial Bus Timing
See
Table 31-8.
Note:
SCL
SDA
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Figure 31-7 on page 376
t
SU;STA
1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t
- 3 t
SS high to tri-state
SCK to out high
SCK high/low
SCK to SS high
SS low to SCK
SCK high/low
Rise/Fall time
Rise/Fall time
SS low to out
SPI Timing Parameters
Description
CLCL
CLCL
SCK period
SCK period
Out to SCK
SCK to out
SCK to out
Setup
Setup
Hold
Hold
for f
for f
CK
CK
t
HD;STA
< 12MHz
> 12MHz
(1)
t
SCL
of
t
LOW
and
LOW
> 308kHz when f
ATmega640/1280/1281/2560/2561
acceptance margin.
Figure 31-8 on page 376
Master
Master
Master
Master
Master
Master
Master
Master
Mode
t
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
HIGH
SCL
t
HD;DAT
requirement.
CK
t
= 8MHz. Still, ATmega640/1280/1281/2560/2561
LOW
4 • t
2 • t
Min
10
t
20
20
ck
ck
ck
SCL
t
SU;DAT
= 100kHz.
for details.
See
50% duty cycle
page 203
Table 21-5 on
0.5 • t
Typ
3.6
10
10
10
10
15
15
10
sck
t
SCL
SCL
SU;STO
- 2/f
- 2/f
t
r
1600
Max
CK
CK
), thus the
), thus f
t
BUF
ns
375
CK
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