ATmega649 Atmel Corporation, ATmega649 Datasheet - Page 10
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ATmega649
Manufacturer Part Number
ATmega649
Description
Manufacturer
Atmel Corporation
Specifications of ATmega649
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega649-16AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATmega649-16MU
Manufacturer:
Atmel
Quantity:
135
Part Number:
ATmega6490-16AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATmega6490-16AU
Manufacturer:
Atmel
Quantity:
135
Company:
Part Number:
ATmega6490-16AUR
Manufacturer:
Atmel
Quantity:
1 500
Company:
Part Number:
ATmega6490A-AU
Manufacturer:
Atmel
Quantity:
1 250
Company:
Part Number:
ATmega6490A-AUR
Manufacturer:
Maxim
Quantity:
43
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6. AVR CPU Core
6.1
6.2
10
Overview
Architectural Overview
ATmega329/3290/649/6490
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Figure 6-1.
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
Control Lines
Instruction
Instruction
Program
Memory
Block Diagram of the AVR Architecture
Register
Decoder
Flash
Program
Counter
and Control
EEPROM
Registrers
I/O Lines
Purpose
General
SRAM
Data Bus 8-bit
Status
32 x 8
Data
ALU
Comparator
I/O Module1
I/O Module 2
I/O Module n
Watchdog
Interrupt
Timer
Analog
Unit
Unit
SPI
2552K–AVR–04/11
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