ATmega649 Atmel Corporation, ATmega649 Datasheet - Page 47
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ATmega649
Manufacturer Part Number
ATmega649
Description
Manufacturer
Atmel Corporation
Specifications of ATmega649
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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135
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Manufacturer:
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Quantity:
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Company:
Part Number:
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Manufacturer:
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Part Number:
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Part Number:
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Part Number:
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Manufacturer:
Maxim
Quantity:
43
10.9
10.9.1
10.9.2
10.10 Register Description
10.10.1
2552K–AVR–04/11
Timed Sequences for Changing the Configuration of the Watchdog Timer
Safety Level 1
Safety Level 2
MCUSR – MCU Status Register
The sequence for changing configuration differs slightly between the two safety levels. Separate
procedures are described for each level.
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit
to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out
period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, and/or
changing the Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written
2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A
timed sequence is needed when changing the Watchdog Time-out period. To change the
Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE
Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with
the WDCE bit cleared. The value written to the WDE bit is irrelevant.
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
Bit
0x35 (0x55)
Read/Write
Initial Value
to WDE regardless of the previous value of the WDE bit.
desired, but with the WDCE bit cleared.
always is set, the WDE must be written to one to start the timed sequence.
R
7
–
0
R
6
–
0
R
5
–
0
JTRF
R/W
4
ATmega329/3290/649/6490
WDRF
R/W
3
See Bit Description
BORF
R/W
2
EXTRF
R/W
1
PORF
R/W
0
MCUSR
47